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IS42S16100C1_07 PDF预览

IS42S16100C1_07

更新时间: 2024-02-26 18:56:44
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美国芯成 - ISSI /
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81页 913K
描述
512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

IS42S16100C1_07 数据手册

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®
IS42S16100C1  
512K Words x 16 Bits x 2 Banks (16-MBIT)  
SYNCHRONOUS DYNAMIC RAM  
ISSI  
NOVEMBER 2006  
FEATURES  
DESCRIPTION  
• Clock frequency: 200, 166, 143 MHz  
ISSI’s 16Mb Synchronous DRAM IS42S16100C1 is  
organized as a 524,288-word x 16-bit x 2-bank for  
improvedperformance. ThesynchronousDRAMs  
achieve high-speed data transfer using pipeline  
architecture. All inputs and outputs signals refer to the  
rising edge of the clock input.  
• Fully synchronous; all signals referenced to a  
positive clock edge  
• Two banks can be operated simultaneously and  
independently  
• Dual internal bank controlled by A11  
(bank select)  
PIN CONFIGURATIONS  
50-Pin TSOP (Type II)  
• Single 3.3V power supply  
• LVTTL interface  
VDD  
DQ0  
DQ1  
GNDQ  
DQ2  
DQ3  
VDDQ  
DQ4  
DQ5  
GNDQ  
DQ6  
DQ7  
VDDQ  
LDQM  
WE  
1
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
GND  
DQ15  
IDQ14  
GNDQ  
DQ13  
DQ12  
VDDQ  
DQ11  
DQ10  
GNDQ  
DQ9  
DQ8  
VDDQ  
NC  
UDQM  
CLK  
CKE  
NC  
A9  
A8  
A7  
A6  
A5  
• Programmable burst length  
– (1, 2, 4, 8, full page)  
2
3
4
5
• Programmable burst sequence:  
Sequential/Interleave  
6
7
8
• 4096 refresh cycles every 64 ms  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
• Random column address every clock cycle  
• Programmable CAS latency (2, 3 clocks)  
• Burst read/write and burst read/single write  
operations capability  
CAS  
RAS  
CS  
• Burst termination by burst stop and  
precharge command  
A11  
A10  
A0  
A1  
• Byte controlled by LDQM and UDQM  
• Industrial temperature up to 143 MHz  
• Packages 400-mil 50-pin TSOP-II, 60-ball fBGA  
• Lead-free package option  
A2  
A3  
VDD  
A4  
GND  
PIN DESCRIPTIONS  
CAS  
ColumnAddressStrobeCommand  
WriteEnable  
A0-A11  
A0-A10  
A11  
Address Input  
WE  
Row Address Input  
Bank Select Address  
Column Address Input  
DataDQ  
LDQM  
UDQM  
VDD  
Lower Bye, Input/Output Mask  
Upper Bye, Input/Output Mask  
Power  
A0-A7  
DQ0 to DQ15  
CLK  
GND  
VDDQ  
GNDQ  
NC  
Ground  
System Clock Input  
Clock Enable  
Power Supply for DQ Pin  
Ground for DQ Pin  
NoConnection  
CKE  
CS  
Chip Select  
RAS  
RowAddressStrobeCommand  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
Rev. D  
11/03/06  

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