®
IS41C4100
IS41LV4100
ISSI
1Meg x 4 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
PRELIMINARYINFORMATION
SEPTEMBER2001
FEATURES
DESCRIPTION
• TTL compatible inputs and outputs
• Refresh Interval: 1024 cycles/16 ms
TheISSI IS41C4100andIS41LV4100are1,048,576x4-bit
high-performance CMOS Dynamic Random Access
Memory. Both products offer accelerated cycle access
EDO Page Mode. EDO Page Mode allows 512 random
accesses within a single row with access cycle time as
short as 10ns per 4-bit word.
• Refresh Mode : RAS-Only, CAS-before-RAS
(CBR), and Hidden
• JEDEC standard pinout
• Single power supply
5V ± 10% (IS41C4100)
3.3V ± 10% (IS41LV4100)
These features make the IS41C4100 and IS41LV4100 ideally
suited for high band-width graphics, digital signal processing,
high-performancecomputingsystems,andperipheralapplications.
• Industrail Temperature Range -40oC to 85oC
TheIS41C4100andIS41LV4100 areavailableina20-pin,
300-mil SOJ package.
KEY TIMING PARAMETERS
PIN CONFIGURATION
20-Pin SOJ
Parameter
-35
35
10
18
12
60
-60
60
Unit
ns
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. Fast Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
15
ns
30
ns
25
ns
I/O0
I/O1
WE
RAS
A9
1
2
3
4
5
20
19
18
17
16
GND
I/O3
I/O2
CAS
OE
110
ns
PIN DESCRIPTIONS
A0-A9
I/O0-I/O3
WE
Address Inputs
Data Inputs/Outputs
Write Enable
A0
A1
6
15
14
13
12
11
A8
A7
A6
A5
A4
7
OE
Output Enable
Row Address Strobe
Column Address Strobe
Power
A2
8
RAS
CAS
VCC
A3
9
Vcc
10
GND
NC
Ground
No Connection
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
1
09/10/01