Datasheet > 存储 > DRAM> IS41C4100-60J

IS41C4100-60J

更新时间： 2024-01-03 20:10:41

品牌	Logo	应用领域
美国芯成 - ISSI		存储内存集成电路光电二极管动态存储器
页数	文件大小	规格书
19页	145K
描述
1Meg x 4 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

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技术参数
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IS41C4100-60J 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOJ	包装说明：	SOJ, SOJ20/26,.34
针数：	20	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.02
风险等级：	5.92	Is Samacsys：	N
访问模式：	FAST PAGE WITH EDO	最长访问时间：	60 ns
其他特性：	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-J20	JESD-609代码：	e0
长度：	17.145 mm	内存密度：	4194304 bit
内存集成电路类型：	EDO DRAM	内存宽度：	4
功能数量：	1	端口数量：	1
端子数量：	20	字数：	1048576 words
字数代码：	1000000	工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	1MX4	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOJ
封装等效代码：	SOJ20/26,.34	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
刷新周期：	1024	座面最大高度：	3.556 mm
自我刷新：	NO	最大待机电流：	0.001 A
子类别：	DRAMs	最大压摆率：	0.075 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

IS41C4100-60J 数据手册

IS41C4100

IS41LV4100

ISSI

2. Using a CAS-before-RAS refresh cycle. CAS-before-

RAS refresh is activated by the falling edge of RAS,

while holding CAS LOW. In CAS-before-RAS refresh

cycle, an internal 10-bit counter provides the row

addresses and the external address inputs are ig-

nored.

Functional Description

The IS41C4100 and IS41LV4100 is a CMOS DRAM

optimized for high-speed bandwidth, low power applica-

tions. During READ or WRITE cycles, each bit is uniquely

addressed through the 19 address bits. The first ten

address bits (A0-A9) are entered as row address and

latter nine bits nine address bits (A0-A8) are entered as

column address. The row address is latched by the Row

Address Strobe (RAS). The column address is latched by

the Column Address Strobe (CAS). RAS is used to latch

the first nine bits and CAS is used the latter nine bits.

CAS-before-RAS is a refresh-only mode and no data

access or device selection is allowed. Thus, the output

remains in the High-Z state during the cycle.

Extended Data Out Page Mode

Memory Cycle

EDOpagemodeoperationpermitsall512columnswithin

a selected row to be randomly accessed at a high data

rate.

A memory cycle is initiated by bring RAS LOW and it is

terminated by returning both RAS and CAS HIGH. To

ensures proper device operation and data integrity any

memory cycle, once initiated, must not be ended or

aborted before the minimum tRAS time has expired. A new

cycle must not be initiated until the minimum precharge

time tRP, tCP has elapsed.

In EDO page mode read cycle, the data-out is held to the

next CAS cycle’s falling edge, instead of the rising edge.

For this reason, the valid data output time in EDO page

mode is extended compared with the fast page mode. In

the fast page mode, the valid data output time becomes

shorter as the CAS cycle time becomes shorter. There-

fore, in EDO page mode, the timing margin in read cycle

is larger than that of the fast page mode even if the CAS

cycle time becomes shorter.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,

whichever occurs last, while holding WE HIGH. The

column address must be held for a minimum time speci-

fied by tAR. Data Out becomes valid only when tRAC, tAA,

tCAC and tOEA are all satisfied. As a result, the access time

is dependent on the timing relationships between these

parameters.

InEDOpagemode,duetotheextendeddatafunction,the

CAS cycle time can be shorter than in the fast page mode

if the timing margin is the same.

The EDO page mode allows both read and write opera-

tions during one RAS cycle, but the performance is

equivalent to that of the fast page mode in that case.

Write Cycle

Power-On

A write cycle is initiated by the falling edge of CAS and

WE, whichever occurs last. The input data must be valid

at or before the falling edge of CAS or WE, whichever

occurs last.

After application of the VCC supply, an initial pause of

200 µs is required followed by a minimum of eight initial-

ization cycles (any combination of cycles containing a

RASsignal).

Refresh Cycle

During power-on, it is recommended that RAS track with

VCC or be held at a valid VIH to avoid current surges.

To retain data, 1024 refresh cycles are required in each

16 ms period. There are two ways to refresh the memory.

1. By clocking each of the 1024 row addresses (A0

through A9) with RAS at least once every 16 ms. Any

read, write, read-modify-write or RAS-only cycle re-

freshes the addressed row.

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00A

09/10/01

1 2 345 6 7...19

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与IS41C4100-60J相关器件

型号	品牌	描述	获取价格	数据表
IS41C4100-60JI	ISSI	1Meg x 4 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IS41C44002	ICSI	4Mx4 bit Dynamic RAM with EDO Page Mode	获取价格
IS41C44002	ISSI	4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IS41C44002-50J	ISSI	4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IS41C44002-50JI	ISSI	4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IS41C44002-50T	ETC	x4 EDO Page Mode DRAM	获取价格

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