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IMP8980DP/T PDF预览

IMP8980DP/T

更新时间: 2024-02-28 18:21:35
品牌 Logo 应用领域
IMP 开关PC
页数 文件大小 规格书
14页 137K
描述
PCM Digital Switch

IMP8980DP/T 技术参数

生命周期:Obsolete零件包装代码:LCC
包装说明:,针数:44
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.29JESD-30 代码:S-PQCC-J44
端子数量:44封装主体材料:PLASTIC/EPOXY
封装形状:SQUARE封装形式:CHIP CARRIER
认证状态:Not Qualified表面贴装:YES
电信集成电路类型:DIGITAL TIME SWITCH端子形式:J BEND
端子位置:QUAD

IMP8980DP/T 数据手册

 浏览型号IMP8980DP/T的Datasheet PDF文件第2页浏览型号IMP8980DP/T的Datasheet PDF文件第3页浏览型号IMP8980DP/T的Datasheet PDF文件第4页浏览型号IMP8980DP/T的Datasheet PDF文件第6页浏览型号IMP8980DP/T的Datasheet PDF文件第7页浏览型号IMP8980DP/T的Datasheet PDF文件第8页 
switch and a second IMP8980D for  
communication with the line interface  
circuits.  
A larger digital switching system may be  
designed by cascading a number of  
IMP8980Ds. Figure 9 shows four  
IMP8980Ds arranged in a non-blocking  
configuration which can switch any  
channel on any of the ST-BUS inputs to  
any channel on the ST-BUS outputs.  
For convenience, a 4MHz crystal  
oscillator has been used rather than a  
4.096MHz clock, as both are within the  
limits of the chip’s specifications. The RC  
delay used with the 393 counters ensures a  
sufficient hold time for the FP signal, but  
the values used may have to be changed if  
faster 393 counters become available.The  
chip is shown as memory mapped into the  
MEK6802D3 system. Chip addresses  
00-3F correspond to processor addresses  
2000-203F. Delay through the address  
decoder requires the VMA signal to be  
used twice to remove glitches. The  
Application Circuit with 6802  
Processor  
Figure 10 shows an example of a  
complete circuit which may be used to  
evaluate the chip.  
MEK6802D3 board uses a 10Kpullup  
on the MR pin, which would have to be  
incorporated into the circuit if the board  
was replaced by a processor.  
Figure 6 - Connection Memory Low Bits  
Stream  
Address  
Bits  
Channel  
Address  
Bits  
7
6
5
4
3
2
1
0
BIT  
NAME  
DESCRIPTION  
7-5*  
Stream *  
Address  
Bits  
The number expressed in binary notation on these 3 bits is  
the number of the ST-BUS stream for the source of the connection.  
Bit 7 is the most significant bit. e.g., if bit 7 is 1, bit 6 is 0 and bit 5  
is 0, then the source of the connection is a channel on STi4.  
The number expressed in binary notation on these 5 bits is  
the number of the channel which is the source of the connection  
(The ST-BUS stream where the channel lies is defined by bits 7,  
6 and 5.). Bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is  
0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the  
connection is channel 19.  
4-0*  
Channel  
Address  
Bits*  
* If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1,  
then the entire 8 bits are output on the channel and stream associated with this location.  
Otherwise, the bits are used as indicated to define the source of the connection which is  
output on the channel and stream associated with this location.  
5

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