Datasheet > IMP1232LPSN

IMP1232LPSN

更新时间： 2024-02-03 02:42:28

品牌	Logo	应用领域
IMP		/
页数	文件大小	规格书
7页	106K
描述
5V レP Power Suppl er Supply Monit y Monitor and or and Reset Cir eset Circuit

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IMP1232LPSN 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.71
Is Samacsys：	N	Base Number Matches：	1

IMP1232LPSN 数据手册

IMP1232LP/LPS

Application Information

Supply Voltage Monitor

Reset Signal Polarity and Output Stage Structure

TRIP Point Voltage (V)

Tolerance

Select

Tolerance

10%

Min

4.25

4.5

Nominal

4.37

Max

4.49

4.74

RESET is an active LOW signal. It is developed with an open

drain driver. If a pullup resistor is required, typical values are

10kΩ to 50kΩ.

TOL = V

TOL = GND

4.62

1232_t02.eps

RESET is an active High signal developed by a CMOS push-pull

output stage and is the logical opposite to RESET.

Manual Reset Operation

Push-button switch input, PBRST, allows the user to override the

internal trip point detection circuits and issue reset signals. The

pushbutton input is debounced and is normally pulled HIGH

through an internal 40kΩ resistor.

Trip Point Tolerance Selection

With TOL connected to V_CC, RESET and RESET become active

whenever V_CCfalls below 4.5V. RESET and RESET become active

when V_CCfalls below 4.75V if TOL is connected to ground.

When PBRST is held LOW for the minimum time t_PB, both resets

become active and remain active for approximately a minimum

time period of 250ms after PBRST returns HIGH.

After V_CChas risen above the trip point set by TOL, RESET and

RESET remain active for a minimum time period of 250ms.

The debounced input is guaranteed to recognize pulses greater

than 20ms. No external pull-up resistor is required, since PBRST

is pulled HIGH by an internal 40kΩ resistor.

On power-down, once V_CCfalls below the reset threshold RESET

stays LOW and is guaranteed to be 0.4V or less until V_CCdrops

below 1.2V. The active HIGH reset signal is valid down to a V_CC

level of 1.2V also.

The PBRST can be driven from a TTL or CMOS logic line or short-

ed to ground with a mechanical switch.

t_R

t_PB

PBRST

4.75V

V_CCTP

t_PDLY

4.25V

t_RST

V_CC

t_RPU

RESET

V_OH

V_OL

V_OH

RESET

1232_08.eps

Figure 3. Timing Diagram: Pushbutton Reset

V_OL

RESET

1232_05.eps

Figure 1. Timing Diagram: Power Up

IMP1232LP/LPS

PBRST

V_CC

t_F

V_CC

4.75V

µP

V_CCTP

4.25V

TOL

RESET

GND RESET

RESET

1232_06.eps

t_RPD

Figure 4. Application Circuit: Pushbutton Reset

RESET

V_OH

V_OL

RESET

1232_04.eps

Figure 2. Timing Diagram: Power Down

408-432-9100/ www.impweb.com

1 2 345 6 7

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