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IMISG528BX PDF预览

IMISG528BX

更新时间： 2024-01-09 00:54:49
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
12页 119K
描述
Clock Generator, 120MHz, CMOS, PDSO16, 0.300 INCH, PLASTIC, SOIC-16

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IMISG528BX 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP,
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.8JESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.3 mm
湿度敏感等级：3端子数量：16
最高工作温度：70 °C最低工作温度：
最大输出时钟频率：120 MHz封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
主时钟/晶体标称频率：48 MHz认证状态：Not Qualified
座面最大高度：2.65 mm最大供电电压：5.5 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：7.5 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

IMISG528BX 数据手册

 浏览型号IMISG528BX的Datasheet PDF文件第1页浏览型号IMISG528BX的Datasheet PDF文件第2页浏览型号IMISG528BX的Datasheet PDF文件第4页浏览型号IMISG528BX的Datasheet PDF文件第5页浏览型号IMISG528BX的Datasheet PDF文件第6页浏览型号IMISG528BX的Datasheet PDF文件第7页 
SG521/22/24/28  
Spread Spectrum Clock Generator  
Approved Product  
Pin Configuration  
VDD  
OSCin  
OSCout  
VSS  
1
2
3
4
5
6
7
8
16  
15  
TEST  
VDD  
SG521  
---------- 14  
SG522  
MPCLK/S3  
VSS  
13  
----------  
SG524  
----------  
SG528  
S4  
12  
11  
10  
9
PRCLK/S2  
VSS  
VDD  
S0  
SS-SEL  
SSON  
S1  
Figure 2. SG521/22/24/28 SOIC Package Pin Assignment  
Pin Description  
Pin  
#
Signal  
Name  
VDD  
I/O Default  
Description  
State  
1
P
I
Power Positive Power Supply.  
2
3
4
5
OSCin  
OSCout  
VSS  
N/A  
N/A  
GND.  
1
Input pin of on-chip reference oscillator.  
O
P
I
Output pin of on-chip reference oscillator. If Crystal Oscillator is used, this pin is left unconnected.  
Power Supply Ground.  
S4  
Digital logic input used to select required crystal input frequency range, frequency spread clock  
(PRCLK) and non-spread clock MPCLK output frequencies. This pin has internal 150 K ohm pull-up  
resistor to VDD. Refer to Frequency Selection Tables for Truth Table.  
6
7
VDD  
S0  
P
I
Positive Power Supply  
0
0
1
1
Digital logic input used to select required crystal input frequency range, frequency spread clock  
(PRCLK) and non-spread clock MPCLK output frequencies. This pin has internal 150 K ohm pull-down  
resistor to GND. Refer to Frequency Selection Tables for Truth Table.  
8
9
S1  
I
I
I
Digital logic input used to select required crystal input frequency range, frequency spread clock  
(PRCLK) and non-spread clock MPCLK output frequencies. This pin has internal 150 K ohm pull-down  
resistor to GND. Refer to Frequency Selection Tables for Truth Table.  
SSON  
SS-SEL  
Input digital control pin used to enable or disable the frequency modulation function at PRCLK Output  
(Pin-12). When this pin is low (GND) spread function is on. When high (VDD), spread function is turned-  
off. This pin has 150 K ohm internal pulled-up to VDD.  
10  
Used to select total Frequency Modulation (Spread) amount. The spread is either 1.25%(Narrow) or  
3.25%(Wide). Both spreads are down-center with respect to output frequency at PRCLK (Pin-12). Refer  
to Frequency and Spread selection Tables for the Spread selection logic states. This pin has 150 K  
internal pull-up resistor to VDD.  
11  
12  
VSS  
P
GND.  
1
Power Supply Ground  
PRCLK/S2 I/O  
Bi-directional pin used to share input control and output drive function. During power-on, this pin is a  
digital input and latches that state (High or Low) into an internal register as a valid S2 state. After power  
has reached a pre-determined level, pin 12 becomes the driver for the PRCLK modulated output clock.  
This pin has 150 K ohm internal pull-up resistor to VDD. For proper operation, an external 4.7 K ohm  
resistor connected to VDD or VSS is required. Refer to Frequency Selection Truth Tables for proper  
operation.  
13  
14  
VSS  
P
GND.  
1
Power Supply Ground  
MPCLK/S3 O/I  
Bi-directional pin used to share input control and output drive function. During power-on, this pin is a  
digital input and latches that state (High or Low) into an internal register as a valid S3 state. After power  
has reached a pre-determined level, pin 14 becomes the driver for the MPCLK non-modulated output  
clock. This pin has 150 K ohm internal pull-up resistor to VDD. Refer to Frequency Selection Truth  
Tables for proper operation.  
15  
16  
VDD  
P
I
Power Positive Power Supply  
Provides Power-Down and Hi-Z function when used in conjunction with S0 and S1 digital inputs. This  
pin has internal pull-down to GND. Refer to Frequency Selection Truth Tables for proper operation.  
TEST  
0
INTERNATIONAL MICROCIRCUITS,INC. 525 LOS COCHES ST.,  
MILPITAS, CA 95035 408-263-6300, FAX 408-263-6571  
http:/www.imicorp.com  
Rev. 2.0  
5/25/2000  
Page 3 of 12  
1234567...12

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