List of Tables
Table 1: Pin Description ............................................................................................................................................................................................. 11
Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 15
Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 16
Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 18
Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 20
Table 6: Input Clock Selection ................................................................................................................................................................................... 21
Table 7: External Fast Selection ................................................................................................................................................................................ 21
Table 8: ‘n’ Assigned to the Input Clock ..................................................................................................................................................................... 22
Table 9: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 22
Table 10: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 23
Table 11: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 23
Table 12: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 24
Table 13: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 26
Table 14: T0 DPLL Operating Mode Control ............................................................................................................................................................... 27
Table 15: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 28
Table 16: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 29
Table 17: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 30
Table 18: Holdover Frequency Offset Read ................................................................................................................................................................ 30
Table 19: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 31
Table 20: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 33
Table 21: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 34
Table 22: Outputs on OUT1 & OUT2 if Derived from T0 DPLL Outputs ..................................................................................................................... 34
Table 23: Outputs on OUT1 & OUT2 if Derived from T0/T4 APLL .............................................................................................................................. 35
Table 24: Frame Sync Input Signal Selection .............................................................................................................................................................. 36
Table 25: Synchronization Control ............................................................................................................................................................................... 36
Table 26: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 37
Table 27: Related Bit / Register in Chapter 3.14 ......................................................................................................................................................... 38
Table 28: Definition of S/Sr and P Conditions ............................................................................................................................................................. 40
Table 29: Timing Definition .......................................................................................................................................................................................... 42
Table 30: JTAG Timing Characteristics ....................................................................................................................................................................... 43
Table 31: Register List and Map .................................................................................................................................................................................. 44
Table 32: Absolute Maximum Rating ........................................................................................................................................................................... 99
Table 33: Recommended Operation Conditions .......................................................................................................................................................... 99
Table 34: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 100
Table 35: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 100
Table 36: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 100
Table 37: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 101
Table 38: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 103
Table 39: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 104
Table 40: Output Clock Jitter Generation .................................................................................................................................................................. 105
Table 41: Output Clock Phase Noise ......................................................................................................................................................................... 106
Table 42: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 106
Table 43: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 106
Table 44: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 106
Table 45: Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 107
Table 46: T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 107
Table 47: Input/Output Clock Timing ......................................................................................................................................................................... 109
Table 48: Output Clock Timing .................................................................................................................................................................................. 110
List of Tables
5
August 21, 2007
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