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IDT82V3203BNL PDF预览

IDT82V3203BNL

更新时间: 2024-01-20 11:38:33
品牌 Logo 应用领域
艾迪悌 - IDT 电信电信集成电路
页数 文件大小 规格书
118页 1288K
描述
Telecom Circuit, 1-Func, CMOS, PQCC68, PLASTIC, VFQFPN-68

IDT82V3203BNL 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN,针数:68
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.87JESD-30 代码:S-PQCC-N68
JESD-609代码:e0长度:10 mm
湿度敏感等级:3功能数量:1
端子数量:68最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):255
认证状态:Not Qualified座面最大高度:1 mm
标称供电电压:3.3 V表面贴装:YES
技术:CMOS电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:10 mmBase Number Matches:1

IDT82V3203BNL 数据手册

 浏览型号IDT82V3203BNL的Datasheet PDF文件第1页浏览型号IDT82V3203BNL的Datasheet PDF文件第2页浏览型号IDT82V3203BNL的Datasheet PDF文件第4页浏览型号IDT82V3203BNL的Datasheet PDF文件第5页浏览型号IDT82V3203BNL的Datasheet PDF文件第6页浏览型号IDT82V3203BNL的Datasheet PDF文件第7页 
Table of Contents  
FEATURES.............................................................................................................................................................................. 7  
HIGHLIGHTS.................................................................................................................................................................................................... 7  
MAIN FEATURES ............................................................................................................................................................................................ 7  
OTHER FEATURES......................................................................................................................................................................................... 7  
APPLICATIONS....................................................................................................................................................................... 7  
DESCRIPTION......................................................................................................................................................................... 8  
FUNCTIONAL BLOCK DIAGRAM.......................................................................................................................................... 9  
1 PIN ASSIGNMENT ........................................................................................................................................................... 10  
2 PIN DESCRIPTION .......................................................................................................................................................... 11  
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 15  
3.1 RESET ........................................................................................................................................................................................................... 15  
3.2 MASTER CLOCK .......................................................................................................................................................................................... 15  
3.3 INPUT CLOCKS & FRAME SYNC SIGNALS ............................................................................................................................................... 16  
3.3.1 Input Clocks .................................................................................................................................................................................... 16  
3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 16  
3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 17  
3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 19  
3.5.1 Activity Monitoring ......................................................................................................................................................................... 19  
3.5.2 Frequency Monitoring ................................................................................................................................................................... 20  
3.6 DPLL INPUT CLOCK SELECTION .............................................................................................................................................................. 21  
3.6.1 External Fast Selection .................................................................................................................................................................. 21  
3.6.2 Forced Selection ............................................................................................................................................................................ 22  
3.6.3 Automatic Selection ....................................................................................................................................................................... 22  
3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 23  
3.7.1 DPLL Locking Detection ................................................................................................................................................................ 23  
3.7.1.1 Fast Loss .......................................................................................................................................................................... 23  
3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 23  
3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 23  
3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 23  
3.7.2 Locking Status ............................................................................................................................................................................... 23  
3.7.3 Phase Lock Alarm .......................................................................................................................................................................... 23  
3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 25  
3.8.1 Input Clock Validity ........................................................................................................................................................................ 25  
3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 25  
3.8.2.1 Revertive Switch ............................................................................................................................................................... 25  
3.8.2.2 Non-Revertive Switch ....................................................................................................................................................... 25  
3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 25  
3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 27  
3.10 DPLL OPERATING MODE ........................................................................................................................................................................... 29  
3.10.1 Six Operating Modes ..................................................................................................................................................................... 29  
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 29  
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 29  
3.10.1.3 Locked Mode .................................................................................................................................................................... 29  
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 29  
3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 29  
3.10.1.5 Holdover Mode ................................................................................................................................................................. 29  
Table of Contents  
3
August 21, 2007  

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