Datasheet > IDT79R3500

IDT79R3500

更新时间： 2024-02-07 07:06:59

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	145K
描述
RISC CPU PROCESSOR RISCore⑩

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数据手册

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IDT79R3500 数据手册

IDT79R3500 RISC CPU PROCESSOR RISCore

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT79R3500

RISC CPU PROCESSOR

RISCore^™

Integrated Device Technology, Inc.

•

Supports concurrent refill and execution of instructions.

Partial word stores executed as read-modify-write.

6 external interrupt inputs, 2 software interrupts, with

single cycle latency to exception handler routine.

Flexible multiprocessing support on chip with no impact on

uniprocessor designs.

A single chip integrating the R3000 CPU and R3010 FPA

execution units, using the R3000A pinout.

SoftwarecompatiblewithR3000,R2000CPUsandR3010,

R2010 FPAs.

TLB disable feature allowing a simple memory model for

Embedded Applications.

ProgrammableTagbuswidthallowingreducedcostcache.

Hardware Support of Single- and Double-Precision Float-

ing Point Operations that include Add, Subtract, Multiply,

Divide, Comparisons, and Conversions.

Sustained Floating Point Performance of 11 MFlops single

precision LINPACK and 7.3MFLOPS double precision

Supports Full Conformance With IEEE 754-1985 Floating

Point Specification

64-bit FP operation using sixteen 64-bit data registers

Military product compliant to MIL-STD 833, class B

FEATURES:

•

Efficient Pipelining—The CPU’s 5-stage pipeline design

assists in obtaining an execution rate approaching one

instruction per cycle. Pipeline stalls and exceptions are

handled precisely and efficiently.

•

On-Chip Cache Control—The IDT79R3500 provides a

high-bandwidth memory interface that handles separate

external Instruction and Data Caches ranging in size from

4 to 256kBs each. Both caches are accessed during a

single CPU cycle. All cache control is on-chip.

On-Chip Memory Management Unit—A fully-associative,

64-entry Translation Lookaside Buffer (TLB) provides fast

address translation for virtual-to-physical memory map-

ping of the 4GB virtual address space.

•

Dynamically able to switch between Big- and Little- Endian

byte ordering conventions.

Optimizing Compilers are available for C, FORTRAN,

Pascal, COBOL, Ada, PL/1 and C++.

20 through 40MHz clock rates yield up to 32VUPS sus-

tained throughput.

Supports independent multi-word block refill of both the

instruction and data caches with variable block sizes.

•

IDT79R3500 PROCESSOR

CONTROL

Master Pipeline/Bus Control

CPO

FPA

CPU

(System Control Coprocessor)

FPA Registers

Exponent Add Unit

FPA Divide Unit

FPA Multiply Unit

Exception/Control

Registers

General Registers

(32x32)

Memory

Management

Unit Registers

ALU

Local

Control

Logic

Shifter

Integer

Multiplier/Divider

Translation

Lookaside

Buffer

Address Adder

(64 entries)

PC Increment/Mux

Virtual Page Number/

Virtual Address

Data (32+4)

TAG (20+4)

ADDRESS (18)

2871 drw 01

The IDT logo is a registered trademark and RISCore, CEMOS are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OCTOBER 1992

DSC-9054/3

5.3

12 3 4 5 6 7...16

中文翻译

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与IDT79R3500相关器件

型号	品牌	获取价格	描述	数据表
IDT79R3500-20FB	ETC	获取价格	32-Bit Microprocessor
IDT79R3500-20FM	IDT	获取价格	RISC Microprocessor, 32-Bit, 20MHz, CMOS, CQFP172, CAVITY-UP, FP-172
IDT79R3500-20G	ETC	获取价格	32-Bit Microprocessor
IDT79R3500-20GB	ETC	获取价格	32-Bit Microprocessor
IDT79R3500-20GM	ETC	获取价格	32-Bit Microprocessor
IDT79R3500-20MD	ETC	获取价格	32-Bit Microprocessor
IDT79R3500-25FB	ETC	获取价格	32-Bit Microprocessor
IDT79R3500-25FM	ETC	获取价格	32-Bit Microprocessor
IDT79R3500-25G	IDT	获取价格	RISC Microprocessor, 32-Bit, 25MHz, CMOS, CPGA161, CAVITY DOWN, PGA-161
IDT79R3500-25MD	ETC	获取价格	32-Bit Microprocessor

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