IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
The execution engine of the IDT79R3051 family uses a
five-stage pipeline to achieve close-to single cycle execution.
A new instruction can be started in every clock cycle; the
execution engine actually processes five instructions con-
currently (in various pipeline stages). Figure 2 shows the
concurrency achieved by the IDT79R3051 family pipeline.
INTRODUCTION
The IDT IDT79R3051 family is a series of high-perfor-
mance 32-bit microprocessors featuring a high level of inte-
gration which are targeted to high-performance, but cost-
sensitiveembeddedprocessingapplications.TheIDT79R3051
family is designed to bring the high-performance inherent in
the MIPS RISC architecture into low-cost, simplified, power-
sensitive applications.
FunctionalunitswereintegratedontotheCPUcoreinorder
toreducethetotalsystemcost,withoutsignificantlydegrading
system performance. Thus, the IDT79R3051 family is able to
offer35MIPSofintegerperformanceat40MHzwithoutrequir-
ing external SRAM or caches.
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Furthermore,theIDT79R3051familybringsdramaticpower
reductiontotheseembeddedapplications, allowingtheuseof
low-costpackagingfordevicesupto25MHz. TheIDT79R3051
family allows customer applications to bring maximum per-
formance at minimum cost.
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Figure 1 shows a block-level representation of the func-
tional units within the IDT79R3051 family. The IDT79R3051
family could be viewed as the embodiment of a discrete
solution built around the IDT79R3000A or IDT79R3001.
However, by integrating this functionality on a single chip,
dramatic cost and power reductions are achieved.
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Current
CPU
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Currently, there are four members of the IDT79R3051
family. All devices are pin- and software-compatible: the
differences lie in the amount of instruction cache, and in the
memory management capabilities of the processor:
• TheIDT79R3052"E”incorporates8kBofInstructionCache,
and features a full-function Memory Management Unit
(MMU), including a 64-entry fully-associative Translation
LookasideBuffer(TLB).ThisisthesameMMUincorporated
into the IDT79R3000A and IDT79R3001.
Figure 2. R3051 Family 5-Stage Pipeline
System Control Co-Processor
The R3051 family also integrates on-chip the System
Control Co-processor, CP0. CP0 manages both the excep-
tion handling capability of the IDT79R3051 family, as well as
the virtual to physical mapping of the IDT79R3051 family.
There are two versions of the IDT79R3051 family architec-
ture: the Extended Architecture Versions (the IDT79R3051E
and IDT79R3052E) contain a fully associative 64-entry TLB
which maps 4KB virtual pages into the physical address
space. The virtual to physical mapping thus includes kernel
segments which are hard mapped to physical addresses, and
kernel and user segments which are mapped on a page basis
by the TLB into anywhere within the 4GB physical address
space. In this TLB, 8-page translations can be “locked” by the
kernel to insure deterministic response in real-time applica-
tions. These versions thus use the same MMU structure as
that found in the IDT79R3000A and IDT79R3001. Figure 3
shows the virtual-to-physical address mapping found in the
Extended Architecture versions of the processor family.
The Extended Architecture devices allow the system
designertoimplementkernelsoftwaretodynamicallymanage
User task utilization of memory resources, and also allow the
Kernel to effectively “protect” certain resources from user
tasks. These capabilities are important in a number of
embeddedapplications,fromprocesscontrol(whereresource
protection may be extremely important) to X-Window display
systems (where virtual memory management is extremely
important),andcanalsobeusedtosimplifysystemdebugging.
• TheIDT79R3052alsoincorporates8kBofInstructionCache.
However, the MMU is a much simpler subset of the capabili-
ties of the enhanced versions of the architecture, and in fact
does not use a TLB.
• TheIDT79R3051"E”incorporates4KBofInstructionCache.
Additionally, this device features the same full-function
MMU (including TLB file) as the IDT79R3052"E”, and
IDT79R3000A.
• The IDT79R3051 incorporates 4KB of Instruction Cache,
and uses the simpler memory management model of the
IDT79R3052.
An overview of the functional blocks incorporated in these
devices follows.
CPU Core
The CPU core is a full 32-bit RISC integer execution
engine, capable of sustaining close-to single cycle execution
rate. The CPU core contains a five stage pipeline and 32
orthogonal 32-bit registers. The IDT79R3051 family imple-
ments the MIPS ISA. In fact, the execution engine of the
IDT79R3051familyisthesameastheexecutionengineofthe
IDT79R3000A (and IDT79R3001). Thus the IDT79R3051
family is binary-compatible with those CPU engines.
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