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IDT79R3051E-20GB PDF预览

IDT79R3051E-20GB

更新时间: 2024-02-09 01:58:17
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路装置
页数 文件大小 规格书
26页 330K
描述
RISC Microprocessor, 32-Bit, 20MHz, CMOS, CPGA84, CAVITY DOWN, CERAMIC, PGA-84

IDT79R3051E-20GB 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:PGA
包装说明:CAVITY DOWN, CERAMIC, PGA-84针数:84
Reach Compliance Code:not_compliantECCN代码:3A001.A.2.C
HTS代码:8542.31.00.01风险等级:5.86
地址总线宽度:32位大小:32
边界扫描:NO最大时钟频率:40 MHz
外部数据总线宽度:32格式:FIXED POINT
集成缓存:NOJESD-30 代码:S-CPGA-P84
JESD-609代码:e0长度:30.6705 mm
低功率模式:NODMA 通道数量:
外部中断装置数量:6串行 I/O 数:
端子数量:84片上数据RAM宽度:
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装等效代码:PGA84,12X12封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
RAM(字数):0筛选级别:38535Q/M;38534H;883B
座面最大高度:5.207 mm速度:20 MHz
子类别:Microprocessors最大压摆率:350 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
处于峰值回流温度下的最长时间:30宽度:30.6705 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

IDT79R3051E-20GB 数据手册

 浏览型号IDT79R3051E-20GB的Datasheet PDF文件第2页浏览型号IDT79R3051E-20GB的Datasheet PDF文件第3页浏览型号IDT79R3051E-20GB的Datasheet PDF文件第4页浏览型号IDT79R3051E-20GB的Datasheet PDF文件第5页浏览型号IDT79R3051E-20GB的Datasheet PDF文件第6页浏览型号IDT79R3051E-20GB的Datasheet PDF文件第7页 
IDT79R3051 , 79R3051E  
IDT79R3052 , 79R3052E  
IDT79R3051/79R3052  
RISControllers  
Integrated Device Technology, Inc.  
— On-chip DMA arbiter  
FEATURES:  
— Bus Interface minimizes design complexity  
• Single clock input with 40%-60% duty cycle  
• 35 MIPS, over 64,000 Dhrystones at 40MHz  
• Low-cost 84-pin PLCC packaging  
• Instruction set compatible with IDT79R3000A and  
IDT79R3001 MIPS RISC CPUs  
• High level of integration minimizes system cost, power  
consumption  
— IDT79R3000A /IDT79R3001 RISC Integer CPU  
— R3051 features 4KB of Instruction Cache  
— R3052 features 8KB of Instruction Cache  
— All devices feature 2kB of Data Cache  
— “E” Versions (Extended Architecture) feature full  
function Memory Management Unit, including 64-  
entry Translation Lookaside Buffer (TLB)  
— 4-deep write buffer eliminates memory write stalls  
— 4-deep read buffer supports burst refill from slow  
memory devices  
• Flexible bus interface allows simple, low-cost designs  
• 20, 25, 33, and 40MHz operation  
• Complete software support  
— Optimizing compilers  
— Real-time operating systems  
— Monitors/debuggers  
— Floating Point Software  
— Page Description Languages  
BrCond(3:0)  
Clk2xIn  
Clock  
Generator  
Unit  
Master Pipeline Control  
System Control  
Coprocessor  
Integer  
CPU Core  
Exception/Control  
Registers  
General Registers  
(32 x 32)  
Memory Management  
Registers  
ALU  
Shifter  
Mult/Div Unit  
Address Adder  
PC Control  
Int(5:0)  
Translation  
Lookaside Buffer  
(64 entries)  
Virtual Address  
32  
Physical Address Bus  
32  
Instruction  
Cache  
(8kB/4kB)  
Data  
Cache  
(2kB)  
Data Bus  
Bus Interface Unit  
4-deep  
Write  
Buffer  
4-deep  
DMA  
BIU  
Control  
Read  
Arbiter  
Buffer  
Address/  
Data  
DMA Rd/Wr SysClk  
Ctrl Ctrl  
2874 drw 01  
Figure 1. R3051 Family Block Diagram  
The IDT logo is a registered trademark, and RISChipset, RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400 and R4600 are trademarks of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGE  
OCTOBER 2001  
2001 Integrated Device Technology, Inc.  
5.3  
DSC-3000/6  
1

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