Datasheet > IDT74LVCH374ASO8

IDT74LVCH374ASO8

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
6页	64K
描述
Bus Driver, LVC/LCX/Z Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, SOIC-20

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IDT74LVCH374ASO8 数据手册

IDT74LVCH374A

3.3VCMOSOCTALEDGE-TRIGGEREDD-TYPEFLIP-FLOP

EXTENDEDCOMMERCIALTEMPERATURERANGE

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Max.

Unit

Terminal Voltage with Respect to GND

Storage Temperature

– 0.5 to +6.5

– 65 to +150

V^CC

°C

IOUT

DC Output Current

– 50 to +50

– 50

IIK

IOK

ICC

Continuous Clamp Current,

VI < 0 or VO < 0

Continuous Current through

±100

ISS

each VCC or GND

8LVC

SO20-2

SO20-7

SO20-8

SO20-9

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

CLK

CAPACITANCE (TA = +25°C, f = 1.0MHZ)

Symbol

Parameter⁽¹⁾

Conditions

Typ.

Max. Unit

GND

CIN

Input Capacitance

VIN = 0V

4.5

COUT

CI/O

Output

Capacitance

I/O Port

VOUT = 0V

VIN = 0V

5.5

6.5

SOIC/ SSOP/ QSOP/ TSSOP

TOP VIEW

Capacitance

8LVC Link

NOTE:

1. As applicable to the device type.

PIN DESCRIPTION

Pin Names

Description

FUNCTION TABLE (each flip-flop) ⁽¹⁾

CLK

Output-enable Input (Active LOW)

Clock Input

Inputs

CLK

Outputs

(1)

Data Inputs

Data Outputs

↑

NOTE:

1. These pins have “Bus-hold”. All other pins are standard inputs,

outputs, or I/Os.

H or L

Q₀

NOTE:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High-Impedance

↑

Q₀

= LOW-to-HIGH Transition

= Level of Q before the indicated steady-state input conditions

were established.

123 4 5 6

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