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IDT74LVC161APY8 PDF预览

IDT74LVC161APY8

更新时间: 2024-11-21 14:51:27
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 155K
描述
Binary Counter, LVC/LCX/Z Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, SSOP-16

IDT74LVC161APY8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SSOP,
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.31
其他特性:TCO OUTPUT计数方向:UP
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G16
长度:6.2 mm负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):9 ns认证状态:Not Qualified
座面最大高度:2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:5.3 mm最小 fmax:68.97 MHz
Base Number Matches:1

IDT74LVC161APY8 数据手册

 浏览型号IDT74LVC161APY8的Datasheet PDF文件第2页浏览型号IDT74LVC161APY8的Datasheet PDF文件第3页浏览型号IDT74LVC161APY8的Datasheet PDF文件第4页浏览型号IDT74LVC161APY8的Datasheet PDF文件第5页浏览型号IDT74LVC161APY8的Datasheet PDF文件第6页浏览型号IDT74LVC161APY8的Datasheet PDF文件第7页 
3.3V CMOS PRESETTABLE  
SYNCHRONOUS 4-BIT BINARY  
IDT74LVC161A  
COUNTER WITH ASYNCHRONOUS  
RESET, 5 VOLT TOLERANT I/O  
FEATURES:  
counting. Synchronousoperationisprovidedbyhavingallflip-flopsclocked  
simultaniouslyonthepositive-goingedgeoftheclock(CP). Outputs (Q0 to  
Q3) of the counters maybe preset toa highorlowlevel. Alowlevel atthe  
parallelenableinput(PE)disables thecountingactionandcauses thedata  
0.5 MICRON CMOS Technology  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
1.27mm pitch SOIC, 0.635mm pitch QSOP,  
0.65mm pitch SSOP, 0.65mm pitch TSSOP packages  
Extended commercial range of – 40°C to +85°C  
VCC = 3.3V ±0.3V, Normal Range  
atinputs (D toD )tobeloadedintothecounteronthepositive-goingedge  
3
oftheclock0(providedthattheset-upandholdtimerequirements forPEare  
met). Presettakes placeregardless ofthelevels atthecountenableinputs  
(CEPandCET). Alowlevelatthemasterresetinput(MR)setsallfouroutputs  
oftheflip-flops(Q0toQ3)tolowlevelregardlessofthelevelsatCP,PE,CET,  
and CEP inputs (thus providing an asynchronous clear function).  
VCC = 2.3V to 3.6V, Extended Range  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
All inputs, outputs and I/O are 5 Volt tolerant  
Supports hot insertion  
The look-aheadcarrysimplifies serialcascadingofthe counters. Both  
countenable inputs (CEPandCET)mustbe hightocount. The CETinput  
is fedforwardtoenabletheterminalcountoutput(TC). TheTCoutputthus  
enabledwillproduceahighoutputpulseofadurationapproximatelyequal  
to a high level output of Q0. This pulse can be used to enable the next  
cascadedstage. Themaximumclockfrequencyforthecascadedcounters  
isdeterminedbytheCPtoTCpropagationdelayandCEPtoCPset-uptime,  
accordingtothefollowingformula:  
Drive Features for LVC161A:  
High Output Drivers: ±24mA  
Reduced system switching noise  
APPLICATIONS:  
• 5V and 3.3V mixed voltage systems  
Data communication and telecommunication systems  
1
DESCRIPTION:  
fmax  
=
tp(max) (CP to TC) + tsu (CEP to CP)  
TheLVC161Ais ahigh-performance,low-power,low-voltage,Si-gate  
CMOSdevice,superiortomostadvancedCMOS-compatibleTTLfamilies.  
Inputs canbe drivenfromeither3.3Vor5Vdevices.This feature allows  
the use of this device as a translator in a mixed 3.3V/5V supply system.  
The LVC161A is a presettable synchronous binary counter which  
features an internal look-ahead carry and can be used for high-speed  
FUNCTIONALDIAGRAM  
STATEDIAGRAM  
5
3
4
6
0
1
2
3
4
5
6
7
8
D0  
D1  
D2  
D3  
9
PE  
PARALLEL LOAD  
CIRCUITRY  
15  
14  
13  
12  
CET  
CEP  
10  
15  
TC  
7
BINARY COUNTER  
2
1
CP  
MR  
11  
10  
9
Q0  
Q1  
Q2  
Q3  
14  
13  
12  
11  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
OCTOBER 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-5156/-  

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