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IDT74FCT646TQ8 PDF预览

IDT74FCT646TQ8

更新时间: 2024-11-16 15:34:47
品牌 Logo 应用领域
艾迪悌 - IDT 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
8页 107K
描述
Registered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, QSOP-24

IDT74FCT646TQ8 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SSOP,针数:24
Reach Compliance Code:unknown风险等级:5.43
其他特性:DIRECTION CONTROL; SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED OR REAL TIME DATA系列:FCT
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH传播延迟(tpd):9 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
宽度:3.9116 mmBase Number Matches:1

IDT74FCT646TQ8 数据手册

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FAST CMOS OCTAL  
IDT54/74FCT646T/AT/CT  
TRANSCEIVER/  
REGISTER (3-STATE)  
DESCRIPTION:  
FEATURES:  
TheFCT646Tconsists ofabus transceiverwith3-stateD-typeflip-flops  
andcontrolcircuitryarrangedformultiplexedtransmissionofdatadirectly  
from the data bus or from the internal storage registers. The FCT646T  
utilizes the enable control (G) and direction (DIR) pins to control the  
transceiverfunctions.  
• Std., A, and C grades  
Low input and output leakage 1µA (max.)  
• CMOS power levels  
True TTL input and output compatibility:  
VOH = 3.3V (typ.)  
SABandSBAcontrolpinsareprovidedtoselecteitherreal-timeorstored  
data transfer.The circuitryusedforselectcontrolwilleliminate the typical  
decodingglitchthatoccurs ina multiplexerduringthe transitionbetween  
storedandreal-timedata.Alowinputlevelselectsreal-timedataandahigh  
selects storeddata.  
VOL = 0.3V (typ.)  
High Drive outputs (-15mA IOH, 64mA IOL)  
Meets or exceeds JEDEC standard 18 specifications  
Military product compliant to MIL-STD-883, Class B and DESC  
listed (dual marked)  
Data onthe AorBdata bus,orboth,canbe storedinthe internalDflip-  
flops by low-to-high transitions at the appropriate clock pins (CPAB or  
CPBA), regardless ofthe selectorenable controlpins.  
• Power off disable outputs permit "live insertion"  
Available in the following packages:  
Industrial: SOIC, SSOP, QSOP  
Military: CERDIP, LCC  
FUNCTIONALBLOCKDIAGRAM  
G
DIR  
CPBA  
SBA  
CPAB  
SAB  
B REG  
ONE OF EIGHT CHANNELS  
1D  
C1  
A REG  
B1  
A1  
1D  
C1  
TO SEVEN OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
MILITARY AND INDUSTRIAL TEMPERATURE RANGES  
JUNE 2002  
1
© 2002 Integrated Device Technology, Inc.  
DSC-5505/5  

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