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IDT74FCT162344ETEG PDF预览

IDT74FCT162344ETEG

更新时间: 2024-10-28 20:07:39
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
7页 113K
描述
Low Skew Clock Driver, FCT Series, 8 True Output(s), 0 Inverted Output(s), CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56

IDT74FCT162344ETEG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DFP包装说明:DFP,
针数:56Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
系列:FCT输入调节:STANDARD
JESD-30 代码:R-GDFP-F56JESD-609代码:e3
长度:18.415 mm负载电容(CL):50 pF
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:4
反相输出次数:端子数量:56
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):260传播延迟(tpd):3.8 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.5 ns
座面最大高度:2.413 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:FLAT端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:10
宽度:9.652 mmBase Number Matches:1

IDT74FCT162344ETEG 数据手册

 浏览型号IDT74FCT162344ETEG的Datasheet PDF文件第2页浏览型号IDT74FCT162344ETEG的Datasheet PDF文件第3页浏览型号IDT74FCT162344ETEG的Datasheet PDF文件第4页浏览型号IDT74FCT162344ETEG的Datasheet PDF文件第5页浏览型号IDT74FCT162344ETEG的Datasheet PDF文件第6页浏览型号IDT74FCT162344ETEG的Datasheet PDF文件第7页 
FAST CMOS  
ADDRESS/CLOCK  
DRIVER  
IDT54/74FCT162344AT/CT/ET  
DESCRIPTION:  
FEATURES:  
0.5 MICRON CMOS Technology  
The FCT162344AT/CT/ET is a 1:4 address/clock driver built using  
advanced dual metal CMOS technology. This high-speed, low power  
device provides the abilitytofanouttomemoryarrays. Eightbanks,each  
withafanoutof4,and3-statecontrolprovideefficientaddressdistribution.  
One ormore banks maybe usedforclockdistribution.  
Ideal for address line driving and clock distribution  
8 banks with 1:4 fanout and 3-state  
Typical tSK(o) (Output Skew) < 500ps  
Balanced Output Drivers:  
±24mA (commercial)  
±16mA (military)  
The FCT162344AT/CT/ET has balanced output drive with current  
limitingresistors. This offers lowgroundbounce,minimalundershootand  
controlledoutputfalltimesreducingtheneedforexternalseriesterminating  
resistors.  
Reduced system switching noise  
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP  
and 25 mil pitch CERPACK packages  
Extended commercial range of -40°C to +85°C  
VCC = 5V ±10%  
Alarge numberofpowerandgroundpins andTTLoutputswings also  
ensure reduced noise levels. All inputs are designed with hysteresis for  
improvednoise margins.  
Low input and output leakage 1µA (max.)  
FUNCTIONALBLOCKDIAGRAM  
29  
1
OE1  
OE3  
34  
2
B11  
B51  
36  
8
A1  
A5  
30  
6
B14  
B54  
41  
9
B21  
B61  
42  
14  
A2  
A6  
37  
13  
B24  
B64  
56  
28  
OE2  
OE4  
48  
16  
B31  
B71  
43  
15  
A3  
A7  
44  
20  
B34  
B74  
55  
23  
B41  
B81  
49  
21  
A4  
A8  
51  
27  
B44  
B84  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-3069/4  

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