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IDT72V73263DR PDF预览

IDT72V73263DR

更新时间： 2024-10-03 03:04:19
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
37页 309K
描述
Digital Time Switch, PQFP208, 28 X 28 MM, 0.50 MM PITCH, PLASTIC, QFP-208

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IDT72V73263DR 数据手册

 浏览型号IDT72V73263DR的Datasheet PDF文件第2页浏览型号IDT72V73263DR的Datasheet PDF文件第3页浏览型号IDT72V73263DR的Datasheet PDF文件第4页浏览型号IDT72V73263DR的Datasheet PDF文件第5页浏览型号IDT72V73263DR的Datasheet PDF文件第6页浏览型号IDT72V73263DR的Datasheet PDF文件第7页 
3.3 VOLT TIME SLOT INTERCHANGE  
DIGITAL SWITCH WITH RATE  
IDT72V73263  
MATCHING 16,384 X 16,384 CHANNELS  
•
Selectable Synchronous and Asynchronous Microprocessor  
bus timing modes  
IEEE-1149.1 (JTAG) Test Port  
Availablein208-pin(28mmx28mm)PlasticQuadFlatpack(PQFP)  
and 208-pin (17mm x 17mm) Plastic Ball Grid Array (PBGA)  
Operating Temperature Range -40°C to +85°C  
FEATURES:  
•
•
•
Up to 64 serial input and output streams  
•
•
Maximum 16,384 x 16,384 channel non-blocking switching  
Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s,  
16.384Mb/s or 32.768Mb/s  
•
•
•
Rate matching capability: rate selectable on both RX and TX  
in eight groups of 8 streams  
Optional Output Enable Indication Pins for external driver  
High-Z control  
DESCRIPTION:  
TheIDT72V73263hasanon-blockingswitchcapacityof 16,384x16,384  
channelsat32.768Mb/s.With64inputsand64outputs,programmableper  
streamcontrol,andavarietyofoperatingmodes theIDT72V73263is  
designedforthe TDMtime slotinterchange functionineithervoice ordata  
applications.  
•
•
•
•
•
•
•
•
Per-channel Variable Delay Mode for low-latency applications  
Per-channel Constant Delay Mode for frame integrity applications  
Enhanced Block programming capabilities  
TX/RX Internal Bypass  
Automatic identification of ST-BUSand GCI serial streams  
Per-stream frame delay offset programming  
Per-channel High-Impedance output control  
Per-channelprocessormodetoallowmicroprocessor writes toTX  
streams  
Some of the main features of the IDT72V73263 are LOW power 3.3 Volt  
operation,automaticST-BUS® /GCIsensing,memoryblockprogramming,  
simplemicroprocessorinterface,JTAGTestAccessPort(TAP)andper  
stream programmable input offset delay, variable or constant throughput  
modes,outputenableandprocessormode,BERtesting, bypassmode,and  
advancedblockprogramming.  
•
•
Bit Error Rate Testing (BERT) for testing  
Direct microprocessor access to all internal memories  
FUNCTIONALBLOCKDIAGRAM  
RESET  
VCC  
GND  
ODE  
RX0-7  
TX0-TX7  
TX8-15/OEI0-7  
RX8-15  
Data Memory  
MUX  
RX16-23  
TX16-23  
RX24-31  
RX32-39  
RX40-47  
RX48-55  
RX56-63  
Receive  
Serial Data  
Streams  
TX24-31/OEI16-23  
Transmit  
Serial Data  
Streams  
TX32-39  
Connection  
Memory  
TX40-47/OEI32-39  
Internal  
Registers  
TX48-55  
TX56-63/OEI48-55  
JTAG Port  
Timing Unit  
Microprocessor Interface  
C32i F32i  
A0-A15  
BEL  
CS R/W  
DTA/  
BEH  
DS  
S/A  
TMS TDI TCKTDO  
TRST  
D0-D15  
6160 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUSisatrademarkofMitelCorp.  
OCTOBER 2003  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice  
DSC-6160/3  
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