5秒后页面跳转
捷配首页

Datasheet > IDT72V261LA10TFI
IDT72V261LA10TFI PDF预览

IDT72V261LA10TFI

更新时间： 2024-01-26 18:18:44
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
27页 302K
描述
3.3 VOLT CMOS SuperSync FIFO

阅读下载

获取价格

IDT72V261LA10TFI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LFQFP, QFP64,.47SQ,20针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.22
最长访问时间：6.5 ns其他特性：RETRANSMIT
最大时钟频率 (fCLK)：100 MHz周期时间：10 ns
JESD-30 代码：S-PQFP-G64JESD-609代码：e3
长度：10 mm内存密度：147456 bit
内存集成电路类型：OTHER FIFO内存宽度：9
湿度敏感等级：3功能数量：1
端子数量：64字数：16384 words
字数代码：16000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：16KX9可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP64,.47SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.02 A子类别：FIFOs
最大压摆率：0.055 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：10 mmBase Number Matches：1

IDT72V261LA10TFI 数据手册

 浏览型号IDT72V261LA10TFI的Datasheet PDF文件第1页浏览型号IDT72V261LA10TFI的Datasheet PDF文件第2页浏览型号IDT72V261LA10TFI的Datasheet PDF文件第3页浏览型号IDT72V261LA10TFI的Datasheet PDF文件第5页浏览型号IDT72V261LA10TFI的Datasheet PDF文件第6页浏览型号IDT72V261LA10TFI的Datasheet PDF文件第7页 
IDT72V261LA/72V271LA  
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9  
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
PIN DESCRIPTION  
Symbol  
D0–D8  
Name  
Data Inputs  
I/O  
I
Description  
Data inputs for a 9-bit bus.  
MRS  
PRS  
RT  
Master Reset  
Partial Reset  
Retransmit  
I
MRS initializes the read and write pointers to zero and sets the output register to all zeroes.  
During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of  
two programmable flag default settings, and serial or parallel programming of the offset settings.  
I
I
PRS initializes the read and write pointers to zero and sets the output register to all zeroes.  
During Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel),  
and programmable flag settings are all retained.  
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to  
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming  
method, existing timing mode or programmable flag settings. RT is useful to reread data from the first  
physical location of the FIFO.  
FWFT/SI  
WCLK  
First Word Fall  
Through/Serial In  
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset,  
this pin functions as a serial input for loading offset registers  
Write Clock  
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the  
programmable registers for parallel programming, and when enabled by SEN, the rising edge of  
WCLK writes one bit of data into the programmable register for serial programming.  
WEN  
RCLK  
Write Enable  
Read Clock  
I
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.  
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets  
from the programmable registers.  
REN  
OE  
SEN  
LD  
Read Enable  
Output Enable  
Serial Enable  
Load  
I
I
I
I
REN enables RCLK for reading data from the FIFO memory and offset registers.  
OE controls the output impedance of Qn.  
SEN enables serial loading of programmable flag offsets.  
DuringMasterReset, LD selects one oftwopartialflagdefaultoffsets (127or1,023)anddetermines  
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to  
and reading from the offset registers.  
DC  
Don't Care  
I
This pin must be tied to either VCC or GND and must not toggle after Master Reset.  
FF/IR  
Full Flag/  
Input Ready  
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO  
memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there  
is space available for writing to the FIFO memory.  
EF/OR  
PAF  
Empty Flag/  
Output Ready  
O
O
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO  
memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not  
there is valid data available at the outputs.  
Programmable  
Almost-Full Flag  
PAF goes LOW if the number of words in the FIFO memory is more than total word capacity of  
the FIFO minus the full offset value m, which is stored in the Full Offset register. There are two  
possible default values for m: 127 or 1,023.  
PAE  
Programmable  
Almost-Empty Flag  
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored  
in the Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values  
for n can be programmed into the device.  
HF  
Q0–Q8  
Half-Full Flag  
Data Outputs  
Power  
O
O
HF indicates whether the FIFO memory is more or less than half-full.  
Data outputs for a 9-bus  
VCC  
+3.3 Volt power supply pins.  
GND  
Ground  
Ground pins.  
4
1234567...27

下载PDF

与IDT72V261LA10TFI相关器件

型号 品牌 描述 获取价格 数据表
IDT72V261LA15PF IDT 3.3 VOLT CMOS SuperSync FIFO

获取价格
IDT72V261LA15PF8 IDT FIFO, 16KX9, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64

获取价格
IDT72V261LA15PFI IDT 3.3 VOLT CMOS SuperSync FIFO

获取价格
IDT72V261LA15PFI9 IDT FIFO, 16KX9, 10ns, Synchronous, CMOS, PQFP64, TQFP-64

获取价格
IDT72V261LA15TF IDT 3.3 VOLT CMOS SuperSync FIFO

获取价格
IDT72V261LA15TF8 IDT FIFO, 16KX9, 10ns, Synchronous, CMOS, PQFP64, SLIM, TQFP-64

获取价格

与IDT72V261LA10TFI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证