IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
For serial programming, SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programming, WEN together with LD on each rising edge of WCLK,
are used to load the offset registers via Dn. REN together with LD on each
rising edge of RCLK can be used to read the offsets in parallel from Qn
regardless of whether serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: The read and
write pointers are set to the first location of the FIFO. The FWFT pin
selects IDT Standard mode or FWFT mode. The LD pin selects either a
partial flag default setting of 127 with parallel programming or a partial flag
default setting of 1,023 with serial programming. The flags are updated
according to the timing mode and default offsets selected.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag program-
ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timing mode and offsets in effect. PRS is useful for resetting a device in
mid-operation, when reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO more
than once. A LOW on the RT input during a rising RCLK edge initiates a
retransmit operation by setting the read pointer to the first location of the
memory array.
DESCRIPTION (CONTINUED)
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating REN and
enabling a rising RCLK edge, will shift the word from internal memory to
the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked
directly to the data output lines after three transitions of the RCLK signal. A
REN does not have to be asserted for accessing the first word. However,
subsequent words written to the FIFO do require a LOW on REN for
access. The state of the FWFT/SI input during Master Reset determines
the timing mode in use.
For applications requiring more data storage capacity than a single
FIFO can provide, the FWFT timing mode permits depth expansion by
chaining FIFOs in series (i.e. the data outputs of one FIFO are connected
to the corresponding data inputs of the next). No external logic is re-
quired.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF
and FF functions are selected in IDT Standard mode. The IR and OR
functions are selected in FWFT mode. HF, PAE and PAF are always
available for use, irrespective of timing mode.
If, at any time, the FIFO is not actively performing an operation, the chip
will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by acti-
vating control inputs) will immediately take the device out of the power
down state.
PAE and PAF can be programmed independently to switch at any point
in memory. (See Table 1 and Table 2.) Programmable offsets determine
the flag switching threshold and can be loaded by two methods: parallel or
serial. Two default offset settings are also provided, so that PAE can be
set to switch at 127 or 1,023 locations from the empty boundary and the
PAF threshold can be set at 127 or 1,023 locations from the full boundary.
These choices are made with the LD pin during Master Reset.
The IDT72V261LA/72V271LA are fabricated using IDT’s high speed
submicron CMOS technology.
PARTIAL RESET (PRS) MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
IDT
72V261LA
72V271LA
RETRANSMIT (RT)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
FULL FLAG/INPUT READY (FF/IR)
HALF FULL FLAG (HF)
PROGRAMMABLE ALMOST-FULL (PAF)
4673 drw 03
Figure 1. Block Diagram of Single 16,384 x 9 and 32,768 x 9 Synchronous FIFO
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