IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SERIAL PROGRAMMING MODE
registers can be written and then by bringing LD HIGH, write operations
If Serial Programming mode has been selected, as described above, then can be redirected to the FIFO memory. When LD is set LOW again, and
programming of PAE and PAF values can be achieved by using a combi- WEN is LOW, the next offset register in sequence is written to. As an
nation of the LD, SEN, WCLK and SI input pins. Programming PAE and alternative to holding WEN LOW and toggling LD, parallel programming can
PAF proceeds as follows: when LD and SEN are set LOW, data on the SI also be interrupted by setting LD LOW and toggling WEN.
input are written, one bit for each WCLK rising edge, starting with the Empty
Note that the status of a partial flag (PAE or PAF) output is invalid during
Offset LSB and ending with the Full Offset MSB. A total of 26 bits for the the programming process. From the time parallel programming has
IDT72V255LA and 28 bits for the IDT72V265LA. See Figure 13, Serial begun, a partial flag output will not be valid until the appropriate offset word
Loading of Programmable Flag Registers, for the timing diagram for this has been written to the register(s) pertaining to that flag. Measuring from
mode.
Using the serial method, individual registers cannot be programmed se- after two more rising WCLK edges plus tPAF, PAE will be valid after the
lectively. PAE and PAF can show a valid status only after the complete set next two rising RCLK edges plus tPAE plus tSKEW2
of bits (for all offset registers) has been entered. The registers can be The act of reading the offset registers employs a dedicated read offset
reprogrammed as long as the complete set of new offset bits is entered. register pointer. The contents of the offset registers can be read on the
the rising WCLK edge that achieves the above criteria; PAF will be valid
.
When LD is LOW and SEN is HIGH, no serial write to the registers can
occur.
Q
0
-Qn pins when LD is set LOW and REN is set LOW. Data are read via
Qn from the Empty Offset Register on the first LOW-to-HIGH transition of
Write operations to the FIFO are allowed before and during the serial RCLK. Upon the second LOW-to-HIGH transition of RCLK, data are read
programming sequence. In this case, the programming of all offset bits from the Full Offset Register. The third transition of RCLK reads, once
does not have to occur at once. A select number of bits can be written to again, from the Empty Offset Register. See Figure 15, Parallel Read of
the SI input and then, by bringing LD and SEN HIGH, data can be written Programmable Flag Registers, for the timing diagram for this mode.
to FIFO memory via Dn by toggling WEN. When WEN is brought HIGH
It is permissible to interrupt the offset register read sequence with reads
with LD and SEN restored to a LOW, the next offset bit in sequence is writ- or writes to the FIFO. The interruption is accomplished by deasserting
ten to the registers via SI. If an interruption of serial programming is de- REN, LD, or both together. When REN and LD are restored to a LOW level,
sired, it is sufficient either to set LD LOW and deactivate SEN or to set SEN reading of the offset registers continues where it left off. It should be noted,
LOW and deactivate LD. Once LD and SEN are both restored to a LOW and care should be taken from the fact that when a parallel read of the flag
level, serial offset programming continues.
offsets is performed, the data word that was present on the output lines Qn
From the time serial programming has begun, neither partial flag will be will be overwritten.
valid until the full set of bits required to fill all the offset registers has been
Parallel reading of the offset registers is always permitted regardless of
written. Measuring from the rising WCLK edge that achieves the above which timing mode (IDT Standard or FWFT modes) has been selected.
criteria; PAF will be valid after two more rising WCLK edges plus tPAF, PAE
will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2
.
RETRANSMIT OPERATION
It is not possible to read the flag offset values in a serial mode.
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
the read pointer to the first location of memory, then the actual retransmit,
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, which consists of reading out the memory contents, starting at the
then programming of PAE and PAF values can be achieved by using a beginning of memory.
combination of the LD, WCLK , WEN and Dn input pins. ProgrammingPAE
Retransmit setup is initiated by holding RT LOW during a rising RCLK
and PAF proceeds as follows: when LD and WEN are set LOW, data on edge. REN and WEN must be HIGH before bringing RT LOW. At least one
the inputs Dn are written into the Empty Offset Register on the first LOW-to- word, but no more than D –2 words should have been written into the
HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of WCLK, FIFO between Reset (Master or Partial) and the time of Retransmit setup.
data are written into the Full Offset Register. The third transition of WCLK D = 8,192 for the IDT72V255LA and D = 16,384 for the IDT72V265LA.
writes, once again, to the Empty Offset Register. See Figure 14, Parallel In FWFT mode, D = 8,193 for the IDT72V255LA and D = 16,385 for the
Loading of Programmable Flag Registers, for the timing diagram for this IDT72V265LA.
mode.
If IDT Standard mode is selected, the FIFO will mark the beginning of
The act of writing offsets in parallel employs a dedicated write offset the Retransmit setup by setting EF LOW. The change in level will only be
register pointer. The act of reading offsets employs a dedicated read offset noticeable if EF was HIGH before setup. During this period, the internal
register pointer. The two pointers operate independently; however, a read read pointer is initialized to the first location of the RAM array.
and a write should not be performed simultaneously to the offset registers.
A Master Reset initializes both pointers to the Empty Offset (LSB) register. may begin starting with the first location in memory. Since IDT Standard
A Partial Reset has no effect on the position of these pointers. mode is selected, every word read including the first word following
When EF goes HIGH, Retransmit setup is complete and read operations
Write operations to the FIFO are allowed before and during the parallel Retransmit setup requires a LOW on REN to enable the rising edge of RCLK.
programming sequence. In this case, the programming of all offset See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant
registers does not have to occur at one time. One, two or more offset timing diagram.
10
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