IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PIN CONFIGURATION
INDEX
INDEX
29 28 27 26 25
32 31 30
4
3
2
32 31 30
1
5
29
28
27
26
25
24
23
22
21
D
1
RS
1
2
3
4
5
6
7
8
D
1
WEN1
24
23
22
21
20
19
18
17
6
D0
WEN1
WCLK
WEN2/LD
D0
WCLK
WEN2/LD
VCC
PAF
PAE
7
PAF
PAE
8
9
GND
REN1
RCLK
REN2
OE
VCC
GND
Q8
10
11
12
13
Q8
REN1
RCLK
REN2
Q7
Q7
Q6
Q6
Q5
Q5
9
10 11 12 13 14 15 16
14 15 16 17 18 19 20
4092 drw02
4092 drw02a
TQFP (PR32-1, order code: PF)
TOP VIEW
PLCC (J32-1, order code: J)
TOP VIEW
PINDESCRIPTIONS
Symbol
D0-D8
RS
Name
DataInputs
Reset
I/O
Description
I
I
Datainputs fora9-bitbus.
WhenRS is setLOW, internalreadandwrite pointers are settothe firstlocationofthe RAMarray, FF
and PAF go HIGH, and PAE and EF go LOW. A Reset is required before an initial Write after power-up.
WCLK
WriteClock
I
I
DataiswrittenintotheFIFOonaLOW-to-HIGHtransitionofWCLKwhentheWriteEnable(s)areasserted.
WEN1
WriteEnable1
Ifthe FIFOis configuredtohave programmable flags, WEN1 is the onlyWrite Enable pin. WhenWEN1 is
LOW,dataiswrittenintotheFIFOoneveryLOW-to-HIGHtransitionWCLK.IftheFIFOisconfiguredto
have twowrite enables, WEN1 mustbe LOWandWEN2mustbe HIGHtowrite data intothe FIFO. Data
willnotbewrittenintotheFIFOifthe FF is LOW.
WEN2/LD
WriteEnable2/
Load
I
The FIFOis configuredatResettohave eithertwowrite enables orprogrammable flags. IfWEN2/LD
is HIGHatReset,this pinoperates as asecondwriteenable. IfWEN2/LD is LOWatReset,this pinoperates
as acontroltoloadandreadtheprogrammableflagoffsets.IftheFIFOis configuredtohavetwowrite
enables, WEN1 mustbe LOWandWEN2mustbe HIGHtowrite data intothe FIFO. Data willnotbe written
intothe FIFOiftheFF is LOW. IftheFIFOis configuredtohaveprogrammableflags,WEN2/LD is heldLOWto
writeorreadtheprogrammableflagoffsets.
Q0-Q8
RCLK
REN1
DataOutputs
ReadClock
O
I
Dataoutputsfora9-bitbus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted.
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data
will not be read from the FIFO if the EF is LOW.
Read Enable 1
I
REN2
OE
Read Enable 2
OutputEnable
EmptyFlag
I
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
WhenOE is LOW, the data outputbus is active. IfOE is HIGH, the outputdata bus willbe ina high-impedance
I
state.
EF
O
O
O
O
WhenEF is LOW, the FIFOis emptyandfurtherdata reads fromthe outputare inhibited. When EF is
HIGH, the FIFO is not empty. EF is synchronized to RCLK.
WhenPAE isLOW,theFIFOisalmost-emptybasedontheoffsetprogrammedintotheFIFO.Thedefault
offsetatresetis Empty+7.PAE is synchronizedtoRCLK.
WhenPAF isLOW,theFIFOisalmost-fullbasedontheoffsetprogrammedintotheFIFO.Thedefault
offsetatresetisFull-7.PAF issynchronizedtoWCLK.
WhenFF is LOW, the FIFOis fullandfurtherdata writes intothe inputare inhibited. When FF is HIGH, the FIFO
isnotfull.FF issynchronizedtoWCLK.
PAE
PAF
FF
Programmable
Almost-EmptyFlag
Programmable
Almost-FullFlag
Full Flag
VCC
Power
One 3.3V volt power supply pin.
One 0 volt ground pin.
GND
Ground
2