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IDT72V245L10TF PDF预览

IDT72V245L10TF

更新时间: 2024-01-25 21:40:52
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
25页 216K
描述
3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18

IDT72V245L10TF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:QFP, QFP64,.47SQ,20针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.23
最长访问时间:6.5 ns其他特性:EASILY EXPANDABLE IN DEPTH AND WIDTH
最大时钟频率 (fCLK):100 MHz周期时间:10 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:10 mm内存密度:73728 bit
内存集成电路类型:OTHER FIFO内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:64字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX18可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.005 A子类别:FIFOs
最大压摆率:0.03 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

IDT72V245L10TF 数据手册

 浏览型号IDT72V245L10TF的Datasheet PDF文件第19页浏览型号IDT72V245L10TF的Datasheet PDF文件第20页浏览型号IDT72V245L10TF的Datasheet PDF文件第21页浏览型号IDT72V245L10TF的Datasheet PDF文件第23页浏览型号IDT72V245L10TF的Datasheet PDF文件第24页浏览型号IDT72V245L10TF的Datasheet PDF文件第25页 
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM  
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
These FIFOs are ina single Device Configurationwhenthe FirstLoad(FL),  
Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are  
configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or  
(1,1,0) during reset (Figure 28).  
OPERATINGCONFIGURATIONS  
SINGLE DEVICE CONFIGURATION  
AsingleIDT72V205/72V215/72V225/72V235/72V245maybeusedwhen  
theapplicationrequirementsarefor256/512/1,024/2,048/4,096wordsorless.  
RESET (RS)  
WRITE CLOCK (WCLK)  
WRITE ENABLE (WEN)  
LOAD (LD)  
READ CLOCK (RCLK)  
READ ENABLE (REN)  
OUTPUT ENABLE (OE)  
IDT  
72V205  
72V215  
72V225  
72V235  
72V245  
DATA IN (D0 - D17)  
DATA OUT (Q0 - Q17)  
FULL FLAG/INPUT READY (FF/IR)  
PROGRAMMABLE (PAE)  
HALF-FULL FLAG (HF)  
EMPTY FLAG/OUTPUT READY (EF/OR)  
PROGRAMMABLE (PAF)  
FL  
RXI  
WXI  
4294 drw 28  
Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO  
WIDTH EXPANSION CONFIGURATION  
29demonstratesa36-wordwidthbyusingtwoIDT72V205/72V215/72V225/  
72V235/72V245s. Any word width can be attained by adding additional  
IDT72V205/72V215/72V225/72V235/72V245s. TheseFIFOsareinasingle  
DeviceConfigurationwhentheFirstLoad(FL),WriteExpansionIn(WXI)and  
Read Expansion In (RXI) control inputs are configured as (FL, RXI,  
WXI =(0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1)or(1,1,0)duringreset(Figure  
29). Please see the ApplicationNote AN-83.  
Word width may be increased simply by connecting together the control  
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.  
TheexceptionsaretheEmptyFlag/OutputReadyandFullFlag/InputReady.  
BecauseofvariationsinskewbetweenRCLKandWCLK,itispossibleforflag  
assertion and deassertion to vary by one cycle between FIFOs. To avoid  
problemstheusermustcreatecompositeflagsbygatingtheEmptyFlags/Output  
ReadyofeveryFIFO,andseparatelygatingallFullFlags/InputReady. Figure  
RESET (RS)  
RESET (RS)  
DATA IN (D) 36  
18  
18  
READ CLOCK (RCLK)  
WRITE CLOCK (WCLK)  
READ ENABLE (REN)  
OUTPUT ENABLE (OE)  
WRITE ENABLE (WEN)  
LOAD (LD)  
72V205  
72V215  
72V225  
72V235  
72V245  
PROGRAMMABLE (PAF)  
72V205  
72V215  
72V225  
72V235  
72V245  
PROGRAMMABLE (PAE)  
HALF FULL FLAG (HF)  
EMPTY FLAG/OUTPUT  
READY (EF/OR)  
FF/IR  
EF/OR  
FF/IR  
EF/OR  
18  
DATA OUT (Q)  
36  
FULL FLAG/INPUT  
READY (FF/IR)  
FL WXI RXI  
FL WXI RXI  
18  
4294 drw 29  
NOTE:  
1. Do not connect any output control signals directly together.  
Figure 29. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36  
Synchronous FIFO Memory Used in a Width Expansion Configuration  
22  

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