IDT72V245L10PFG

更新时间： 2024-01-13 09:34:17

品牌	Logo	应用领域
艾迪悌 - IDT		存储内存集成电路先进先出芯片时钟
页数	文件大小	规格书
25页	216K
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中文翻译

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数据手册

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IDT72V245L10PFG 数据手册

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO^TM

256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes

totheoutputsQn,onthethirdvalidLOWtoHIGHtransitionofRCLK+tSKEW

afterthefirstwrite. RENdoesnotneedtobeassertedLOW. Inordertoaccess

allotherwords,areadmustbeexecutedusingREN. TheRCLKLOWtoHIGH

transitionafterthelastwordhasbeenreadfromtheFIFO,OutputReady(OR)

willgoHIGHwithatrue read(RCLKwithREN=LOW),inhibitingfurtherread

operations. REN is ignored when the FIFO is empty.

SIGNALDESCRIPTIONS:

INPUTS:

DATA IN (D0 - D17)

Datainputsfor18-bitwidedata.

CONTROLS:

RESET (RS)

OUTPUTENABLE(OE)

ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOW

state. During reset, both internal read and write pointers are set to the first

location.Aresetisrequiredafterpower-upbeforeawriteoperationcantake

place.TheHalf-FullFlag(HF)andProgrammableAlmost-FullFlag(PAF)will

beresettoHIGHaftertRSF.TheProgrammableAlmost-EmptyFlag(PAE)will

beresettoLOWaftertRSF. TheFullFlag (FF)willresettoHIGH. TheEmpty

Flag(EF)willresettoLOWinIDTStandardmodebutwillresettoHIGHinFWFT

mode. Duringreset,theoutputregisterisinitializedtoallzerosandtheoffset

registersareinitializedtotheirdefaultvalues.

WhenOutputEnable (OE)is enabled(LOW), the paralleloutputbuffers

receivedatafromtheoutputregister.WhenOEisdisabled(HIGH),theQoutput

databusisinahigh-impedancestate.

LOAD (LD)

The IDT72V205/72V215/72V225/72V235/72V245 devices contain two

12-bitoffsetregisterswithdataontheinputs,orreadontheoutputs. Whenthe

Load(LD)pinissetLOWandWENissetLOW,dataontheinputsD0-D11is

writtenintotheEmptyOffsetregisteronthefirstLOW-to-HIGHtransitionofthe

Write Clock(WCLK). WhentheLD pinandWEN are heldLOWthendata is

writtenintotheFullOffsetregisteronthesecondLOW-to-HIGHtransitionof

WCLK.ThethirdtransitionofWCLKagainwritestotheEmptyOffsetregister.

However,writingalloffsetregistersdoesnothavetooccuratonetime.One

ortwooffsetregisterscanbewrittenandthenbybringingtheLDpinHIGH,the

FIFOisreturnedtonormalread/writeoperation.WhentheLDpinissetLOW,

andWENisLOW,thenextoffsetregisterinsequenceiswritten.

WRITE CLOCK (WCLK)

AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock

(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH

transitionofWCLK.

The Write andReadClocks canbe asynchronous orcoincident.

WRITE ENABLE (WEN)

WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray

ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored

in the RAM array sequentially and independently of any ongoing read

operation.

WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK

cycle.

To prevent data overflow in the IDT Standard Mode, FF will go LOW,

inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle,

FFwillgoHIGHallowingawritetooccur. TheFFflagisupdatedontherising

edgeofWCLK.

WEN

WCLK

Selection

Writingtooffsetregisters:

EmptyOffset

FullOffset

NoOperation

WriteIntoFIFO

NoOperation

Topreventdata overflow inthe FWFTmode, IR willgoHIGH, inhibiting

furtherwriteoperations. Uponthecompletionofavalidreadcycle,IRwillgo

LOWallowingawritetooccur. TheIRflagisupdatedontherisingedgeofWCLK.

NOTE:

WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.

1. The same selection sequence applies to reading from the registers. REN is enabled and

read is performed on the LOW-to-HIGH transition of RCLK.

READ CLOCK (RCLK)

Figure 2. Writing to Offset Registers

DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead

Clock(RCLK),whenOutputEnable(OE)is setLOW.

The Write andReadClocks canbe asynchronous orcoincident.

EMPTY OFFSET REGISTER

READ ENABLE (REN)

DEFAULT VALUE

WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput

WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdataand

nonewdataisloadedintotheoutputregister. ThedataoutputsQ0-Qnmaintain

the previous data value.

001FH (72V205) 003FH (72V215):

007FH (72V225/72V235/72V245)

FULL OFFSET REGISTER

IntheIDTStandardmode,everywordaccessedatQn,includingthefirst

wordwrittentoanemptyFIFO,mustberequestedusingREN. Whenthelast

wordhasbeenreadfromtheFIFO,theEmptyFlag(EF)willgoLOW,inhibiting

furtherreadoperations. RENisignoredwhentheFIFOisempty. Onceawrite

isperformed,EFwillgoHIGHallowingareadtooccur. TheEFflagisupdated

on the rising edge of RCLK.

DEFAULT VALUE

001FH (72V205) 003FH (72V215):

007FH (72V225/72V235/72V245)

4294 drw 04

NOTE:

1. Any bits of the offset register not being programmed should be set to zero.

Figure 3. Offset Register Location and Default Values

1...6 7 8910 11 12...25

中文翻译

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与IDT72V245L10PFG相关器件

型号	品牌	描述	获取价格	数据表
IDT72V245L10PFG8	IDT	FIFO, 4KX18, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64	获取价格
IDT72V245L10PFI	IDT	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18	获取价格
IDT72V245L10TF	IDT	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18	获取价格
IDT72V245L10TF8	IDT	FIFO, 4KX18, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, STQFP-64	获取价格
IDT72V245L10TF9	IDT	FIFO, 4KX18, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, STQFP-64	获取价格
IDT72V245L10TFG	IDT	FIFO, 4KX18, 6.5ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, STQFP-64	获取价格
IDT72V245L10TFI	IDT	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18	获取价格
IDT72V245L15PF	IDT	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18	获取价格
IDT72V245L15PF9	IDT	FIFO, 4KX18, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64	获取价格
IDT72V245L15PFG	IDT	FIFO, 4KX18, 10ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64	获取价格
IDT72V245L15PFGI	IDT	FIFO, 4KX18, 10ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64	获取价格
IDT72V245L15PFGI8	IDT	FIFO, 4KX18, 10ns, Synchronous, CMOS, PQFP64	获取价格
IDT72V245L15PFI	IDT	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18	获取价格
IDT72V245L15TF	IDT	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18	获取价格
IDT72V245L15TF8	IDT	FIFO, 4KX18, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, STQFP-64	获取价格
IDT72V245L15TF9	IDT	FIFO, 4KX18, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, STQFP-64	获取价格
IDT72V245L15TFGI	IDT	FIFO, 4KX18, 10ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, STQFP-64	获取价格
IDT72V245L15TFGI8	IDT	FIFO, 4KX18, 10ns, Synchronous, CMOS, PQFP64, SLIM, PLASTIC, TQFP-64	获取价格
IDT72V245L15TFI	IDT	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18	获取价格
IDT72V245L15TFI8	IDT	FIFO, 4KX18, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, STQFP-64	获取价格

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