IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OUTPUTENABLE(OE)
SIGNALDESCRIPTIONS
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receivedatafromtheoutputregister. WhenOutputEnable(OE)is disabled
(HIGH),theQoutputdatabusisinahigh-impedancestate.
INPUTS:
DATA IN (D0 - D8)
Datainputsfor9-bitwidedata.
WRITE ENABLE 2/LOAD (WEN2/LD)
This is a dual-purpose pin. The FIFO is configured at Reset to have
programmableflagsortohavetwowriteenables,whichallowsdepthexpansion.
IfWrite Enable 2/Load(WEN2/LD)is sethighatReset(RS =LOW), this pin
operates as asecondWriteEnablepin.
If the FIFO is configured to have two write enables, when Write Enable
(WEN1)is LOW andWrite Enable 2/Load(WEN2/LD)is HIGH, data canbe
loadedintotheinputregisterandRAMarrayontheLOW-to-HIGHtransition
ofeveryWriteClock(WCLK). DataisstoredintheRAMarraysequentiallyand
independently of any on-going read operation.
CONTROLS:
RESET (RS)
ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOWstate.
During reset, both internal read and write pointers are set to the first location.
Aresetis requiredafterpower-upbeforeawriteoperationcantakeplace. The
FullFlag(FF)andProgrammableAlmost-FullFlag(PAF)willberesettoHIGH
aftertRSF. TheEmptyFlag(EF)andProgrammableAlmost-EmptyFlag(PAE)
willbe resettoLOWaftertRSF. Duringreset, the outputregisteris initializedto
all zeros and the offset registers are initialized to their default values.
In this configuration, when Write Enable (WEN1) is HIGH and/or Write
Enable2/Load(WEN2/LD)isLOW,theinputregisterholdsthepreviousdata
and no new data is allowed to be loaded into the register.
WRITE CLOCK (WCLK)
Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther
writeoperations. Uponthecompletionofavalidreadcycle,theFullFlag(FF)
willgoHIGHaftertWFF,allowingavalidwritetobegin. WriteEnable1(WEN1)
and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
TheFIFOisconfiguredtohaveprogrammableflagswhentheWriteEnable
2/Load(WEN2/LD)issetLOWatReset(RS =LOW). TheIDT72V201/72V211/
72V221/72V231/72V241/72V251devices containfour8-bitoffsetregisters
whichcanbeloadedwithdataontheinputs,orreadontheoutputs. SeeFigure
3fordetailsofthesizeoftheregistersandthedefaultvalues.
AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock
(WCLK). DatasetupandholdtimesmustbemetinrespecttotheLOW-to-HIGH
transitionoftheWriteClock(WCLK). TheFullFlag(FF)andProgrammable
Almost-Full Flag (PAF) are synchronized with respect to the LOW-to-HIGH
transitionoftheWriteClock(WCLK).
The Write andReadclocks canbe asynchronous orcoincident.
WRITE ENABLE 1 (WEN1)
IftheFIFOisconfiguredforprogrammableflags,WriteEnable1(WEN1)
istheonlyenablecontrolpin. Inthisconfiguration,whenWriteEnable1(WEN1)
islow,datacanbeloadedintotheinputregisterandRAMarrayontheLOW-
to-HIGHtransitionofeveryWriteClock(WCLK). DataisstoredintheRAMarray
sequentiallyandindependentlyofanyon-goingreadoperation.
Inthisconfiguration,whenWriteEnable1(WEN1)isHIGH,theinputregister
holdsthepreviousdataandnonewdataisallowedtobeloadedintotheregister.
IftheFIFOisconfiguredtohavetwowriteenables,whichallowsfordepth
expansion,therearetwoenablecontrolpins. SeeWriteEnable2paragraph
belowforoperationinthisconfiguration.
If theFIFOisconfiguredtohaveprogrammableflagswhentheWriteEnable
1(WEN1)andWriteEnable2/Load(WEN2/LD)aresetlow,dataontheinputs
DiswrittenintotheEmpty(LeastSignificantBit)OffsetregisteronthefirstLOW-
to-HIGHtransitionoftheWriteClock(WCLK). DataiswrittenintotheEmpty(Most
SignificantBit)OffsetregisteronthesecondLOW-to-HIGHtransitionoftheWrite
Clock(WCLK),intotheFull(LeastSignificantBit)Offsetregisteronthethird
transition,andintotheFull(MostSignificantBit)Offsetregisteronthefourth
transition. Thefifth transitionofthe WriteClock(WCLK)againwritestotheEmpty
(LeastSignificantBit)Offsetregister.
However,writingalloffsetregistersdoesnothavetooccuratonetime. One
ortwooffsetregisterscanbewrittenandthenbybringingtheWriteEnable2/
Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write
operation. WhentheWriteEnable2/Load(WEN2/LD)pinissetLOW,andWrite
Enable1(WEN1)isLOW,thenextoffsetregisterinsequenceiswritten.
Thecontentsoftheoffsetregisterscanbereadontheoutputlineswhenthe
WriteEnable2/Load(WEN2/LD)pinissetlowandbothReadEnables(REN1,
REN2)aresetLOW. DatacanbereadontheLOW-to-HIGHtransitionofthe
Read Clock (RCLK).
Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther
writeoperations. Uponthecompletionofavalidreadcycle,theFullFlag(FF)
willgoHIGHaftertWFF,allowingavalidwritetobegin. WriteEnable1(WEN1)
is ignored when the FIFO is full.
READ CLOCK (RCLK)
DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead
Clock(RCLK).TheEmptyFlag(EF)andProgrammableAlmost-EmptyFlag
(PAE)aresynchronizedwithrespecttotheLOW-to-HIGHtransitionoftheRead
Clock (RCLK).
A read and write should not be performed simultaneously to the offset
registers.
LD
WEN1
WCLK
Selection
Empty Offset (LSB)
The Write andReadclocks canbe asynchronous orcoincident.
0
0
Empty Offset (MSB)
FullOffset(LSB)
Full Offset (MSB)
READ ENABLES (REN1, REN2)
WhenbothReadEnables(REN1,REN2)areLOW,dataisreadfromthe
RAMarraytotheoutputregisterontheLOW-to-HIGHtransitionoftheRead
Clock (RCLK).
WheneitherReadEnable(REN1,REN2)isHIGH,theoutputregisterholds
the previous data and no new data is allowed to be loaded into the register.
WhenallthedatahasbeenreadfromtheFIFO,theEmptyFlag(EF)willgo
LOW,inhibitingfurtherreadoperations.Onceavalidwriteoperationhasbeen
accomplished,theEmptyFlag(EF)willgoHIGHaftertREFandavalidreadcan
begin. TheReadEnables(REN1,REN2)areignoredwhentheFIFOisempty.
0
1
1
0
1
NoOperation
WriteIntoFIFO
NoOperation
1
NOTES:
1. For the purposes of this table, WEN2 = VIH.
2. The same selection sequence applies to reading from the registers. REN1 and REN2
are enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Figure 2. Write Offset Register
5
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