5秒后页面跳转
捷配首页

Datasheet > IDT72V241L10PFG8
IDT72V241L10PFG8 PDF预览

IDT72V241L10PFG8

更新时间： 2024-02-23 20:02:27
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
14页 278K
描述
FIFO, 4KX9, 6.5ns, Synchronous, CMOS, PQFP32, GREEN, PLASTIC, TQFP-32

阅读下载

获取价格

IDT72V241L10PFG8 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LQFP,针数：32
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.38
最长访问时间：6.5 ns周期时间：10 ns
JESD-30 代码：S-PQFP-G32JESD-609代码：e3
长度：7 mm内存密度：36864 bit
内存宽度：9湿度敏感等级：3
功能数量：1端子数量：32
字数：4096 words字数代码：4000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4KX9
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：7 mmBase Number Matches：1

IDT72V241L10PFG8 数据手册

 浏览型号IDT72V241L10PFG8的Datasheet PDF文件第2页浏览型号IDT72V241L10PFG8的Datasheet PDF文件第3页浏览型号IDT72V241L10PFG8的Datasheet PDF文件第4页浏览型号IDT72V241L10PFG8的Datasheet PDF文件第5页浏览型号IDT72V241L10PFG8的Datasheet PDF文件第6页浏览型号IDT72V241L10PFG8的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncFIFO™  
256 x 9, 512 x 9,  
1,024 x 9, 2,048 x 9,  
IDT72V201, IDT72V211  
IDT72V221, IDT72V231  
IDT72V241, IDT72V251  
4,096 x 9 and 8,192 x 9  
are very high-speed, low-power First-In, First-Out (FIFO) memories with  
clockedreadandwritecontrols.Thearchitecture,functionaloperationandpin  
assignments are identical to those of the IDT72201/72211/72221/72231/  
72241/72251,butoperateatapowersupplyvoltage(Vcc)between3.0Vand  
3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-  
bitmemoryarray,respectively.TheseFIFOsareapplicableforawidevariety  
ofdatabufferingneedssuchasgraphics,localareanetworksandinterprocessor  
communication.  
FEATURES:  
• 256 x 9-bit organization IDT72V201  
• 512 x 9-bit organization IDT72V211  
• 1,024 x 9-bit organization IDT72V221  
• 2,048 x 9-bit organization IDT72V231  
• 4,096 x 9-bit organization IDT72V241  
• 8,192 x 9-bit organization IDT72V251  
• 10 ns read/write cycle time  
These FIFOs have 9-bit input and output ports. The input port is  
controlled by a free-running clock (WCLK), and two Write Enable pins  
(WEN1, WEN2). Data is written into the Synchronous FIFO on every  
rising clock edge when the Write Enable pins are asserted. The output  
port is controlled by another clock pin (RCLK) and two Read Enable pins  
(REN1, REN2). The Read Clock can be tied to the Write Clock for single  
clock operation or the two clocks can run asynchronous of one another  
for dual-clock operation. An Output Enable pin (OE) is provided on the  
read port for three-state control of the output.  
TheSynchronousFIFOshavetwofixedflags,Empty(EF)andFull(FF).  
Twoprogrammableflags,Almost-Empty(PAE)andAlmost-Full(PAF),are  
provided for improved system control. The programmable flags default to  
Empty+7andFull-7forPAEandPAF,respectively.Theprogrammableflag  
offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting  
the Load pin (LD).  
• 5V input tolerant  
• Read and Write clocks can be independent  
• Dual-Ported zero fall-through time architecture  
• Empty and Full Flags signal FIFO status  
• Programmable Almost-Empty and Almost-Full flags can be set to  
any depth  
• Programmable Almost-Empty and Almost-Full flags default to  
Empty+7, and Full-7, respectively  
• Output Enable puts output data bus in high-impedance state  
• Advanced submicron CMOS technology  
• Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin  
plastic Thin Quad FlatPack (TQFP)  
• Industrial temperature range (–40°C to +85°C) is available  
• Green parts available, see ordering information  
These FIFOs are fabricated using high-speed submicron CMOS  
technology.  
DESCRIPTION:  
TheIDT72V201/72V211/72V221/72V231/72V241/72V251SyncFIFOs™  
FUNCTIONAL BLOCK DIAGRAM  
D0 - D8  
WCLK  
WEN1  
WEN2  
LD  
INPUT REGISTER  
OFFSET REGISTER  
EF  
FLAG  
LOGIC  
PAE  
PAF  
FF  
WRITE CONTROL  
LOGIC  
RAM ARRAY  
256 x 9, 512 x 9,  
1,024 x 9, 2,048 x 9,  
4,096 x 9, 8,192 x 9  
READ POINTER  
WRITE POINTER  
READ CONTROL  
LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
RCLK  
REN1  
REN2  
RS  
OE  
4092 drw 01  
Q0 - Q8  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2013  
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4092/6  
1234567...14

下载PDF

与IDT72V241L10PFG8相关器件

型号 品牌 描述 获取价格 数据表
IDT72V241L10PFI IDT 3.3 VOLT CMOS SyncFIFO⑩ 256 x 9, 512 x 9, 1,0

获取价格
IDT72V241L15 IDT 3.3 VOLT CMOS SyncFIFO⑩ 256 x 9, 512 x 9, 1,0

获取价格
IDT72V241L15J IDT 3.3 VOLT CMOS SyncFIFO⑩ 256 x 9, 512 x 9, 1,0

获取价格
IDT72V241L15J8 IDT FIFO, 4KX9, 10ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

获取价格
IDT72V241L15JI IDT 3.3 VOLT CMOS SyncFIFO⑩ 256 x 9, 512 x 9, 1,0

获取价格
IDT72V241L15JI8 IDT FIFO, 4KX9, 10ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

获取价格

与IDT72V241L10PFG8相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证