3.3 VOLT CMOS SyncFIFO™
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
IDT72V201, IDT72V211
IDT72V221, IDT72V231
IDT72V241, IDT72V251
4,096 x 9 and 8,192 x 9
FEATURES:
clockedreadandwritecontrols.Thearchitecture,functionaloperationandpin
assignments are identical to those of the IDT72201/72211/72221/72231/
72241/72251,butoperateatapowersupplyvoltage(Vcc)between3.0Vand
3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit
memoryarray,respectively.TheseFIFOsareapplicableforawidevarietyof
databufferingneedssuchasgraphics,localareanetworksandinterprocessor
communication.
These FIFOs have 9-bit input and output ports. The input port is
controlled by a free-running clock (WCLK), and two Write Enable pins
(WEN1,WEN2). Datais writtenintotheSynchronous FIFOoneveryrising
clock edge when the Write Enable pins are asserted. The output port is
controlledbyanotherclockpin(RCLK)andtwoReadEnable pins (REN1,
• 256 x 9-bit organization IDT72V201
• 512 x 9-bit organization IDT72V211
• 1,024 x 9-bit organization IDT72V221
• 2,048 x 9-bit organization IDT72V231
• 4,096 x 9-bit organization IDT72V241
• 8,192 x 9-bit organization IDT72V251
• 10 ns read/write cycle time
• 5V input tolerant
• Read and Write clocks can be independent
• Dual-Ported zero fall-through time architecture
• Empty and Full Flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags can be set to REN2). The Read Clock can be tied to the Write Clock for single clock
any depth
operationorthe twoclocks canrunasynchronous ofone anotherfordual-
clockoperation. AnOutputEnable pin(OE)is providedonthe readport
forthree-state controlofthe output.
• Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
• Output Enable puts output data bus in high-impedance state
• Advanced submicron CMOS technology
• Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin
plastic Thin Quad FlatPack (TQFP)
The Synchronous FIFOs have twofixedflags, Empty(EF)andFull(FF).
Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are
provided for improved system control. The programmable flags default to
Empty+7andFull-7forPAEandPAF,respectively.Theprogrammableflag
offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting
the Load pin (LD).
• Industrial temperature range (–40°C to +85°C) is available
These FIFOs are fabricated using IDT's high-speed submicron CMOS
technology.
DESCRIPTION:
TheIDT72V201/72V211/72V221/72V231/72V241/72V251SyncFIFOs™
are very high-speed, low-power First-In, First-Out (FIFO) memories with
FUNCTIONAL BLOCK DIAGRAM
D0 - D8
WCLK
WEN1
WEN2
LD
INPUT REGISTER
OFFSET REGISTER
EF
FLAG
LOGIC
PAE
PAF
FF
WRITE CONTROL
LOGIC
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
READ POINTER
WRITE POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
REN1
REN2
RS
OE
4092 drw 01
Q0 - Q8
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEBRUARY 2002
1
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4092/3