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IDT72801L10PF8 PDF预览

IDT72801L10PF8

更新时间: 2024-01-15 11:43:43
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
16页 154K
描述
FIFO, 256X9, 6.5ns, Synchronous, CMOS, PQFP64, TQFP-64

IDT72801L10PF8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP-64针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.2
最长访问时间:6.5 ns最大时钟频率 (fCLK):100 MHz
周期时间:10 nsJESD-30 代码:S-PQFP-G64
JESD-609代码:e0长度:14 mm
内存密度:2304 bit内存集成电路类型:OTHER FIFO
内存宽度:9湿度敏感等级:3
功能数量:2端子数量:64
字数:256 words字数代码:256
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256X9
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP64,.6SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:5 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.01 A
子类别:FIFOs最大压摆率:0.06 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT72801L10PF8 数据手册

 浏览型号IDT72801L10PF8的Datasheet PDF文件第6页浏览型号IDT72801L10PF8的Datasheet PDF文件第7页浏览型号IDT72801L10PF8的Datasheet PDF文件第8页浏览型号IDT72801L10PF8的Datasheet PDF文件第10页浏览型号IDT72801L10PF8的Datasheet PDF文件第11页浏览型号IDT72801L10PF8的Datasheet PDF文件第12页 
Commercial And Industrial Temperature Range  
IDT72801/728211/72821/72831/72841/72851  
tRS  
RSA (RSB)  
tRSS  
tRSS  
tRSS  
t
RSR  
RSR  
RENA1, RENA2  
(RENB1, RENB2)  
t
WENA1  
(WENB1)  
tRSR  
(1)  
WENA2/LDA  
(WENB2/LDB)  
tRSF  
EFA, PAEA  
(EFB, PAEB)  
tRSF  
FFA, PAFA  
(FFB, PAFB)  
tRSF  
(2)  
OEA (OEB) = 1  
QA  
0
- QA  
8
(QB  
0
- QB8)  
3034 drw 05  
OEA (OEB) = 0  
NOTES:  
1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second write enable pin. Holding WENA2/LDA (WENB2/LDB) LOW  
during reset will make the pin act as a load enable for the programmable flag offset registers.  
2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.  
3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.  
Figure 4. Reset Timing  
tCLK  
tCLKH  
tCLKL  
WCLKA (WCLKB)  
tDH  
tDS  
DA  
0
- DA  
8
(DB0  
- DB8)  
DATA IN VALID  
t
ENH  
ENH  
t
ENS  
WENA1  
(WENB1)  
NO OPERATION  
NO OPERATION  
t
tENS  
WENA2 (WENB2)  
(If Applicable)  
t
WFF  
tWFF  
FFA  
(FFB)  
(1)  
SKEW1  
t
RCLKA (RCLKB)  
RENA1, RENA2  
(RENB1, RENB2)  
3034 drw 06  
NOTE:  
1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time between  
the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change state until the next WCLKA (WCLKB) edge.  
Figure 5. Write Cycle Timing  
9

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