IDT723653L15PF8 PDF预览

IDT723653L15PF8

更新时间: 2025-09-18 19:15:15
品牌 Logo 应用领域
瑞萨 - RENESAS 存储
页数 文件大小 规格书
30页 335K
描述
存储容量(Mb):72K(2K x 36);内存数据长度(bit):2K ;字编码数(k):2K ;元器件封装:128-TQFP;

IDT723653L15PF8 数据手册

 浏览型号IDT723653L15PF8的Datasheet PDF文件第2页浏览型号IDT723653L15PF8的Datasheet PDF文件第3页浏览型号IDT723653L15PF8的Datasheet PDF文件第4页浏览型号IDT723653L15PF8的Datasheet PDF文件第5页浏览型号IDT723653L15PF8的Datasheet PDF文件第6页浏览型号IDT723653L15PF8的Datasheet PDF文件第7页 
CMOS SyncFIFOTM WITH BUS-MATCHING  
IDT723663  
IDT723673  
4,096 x 36  
8,192 x 36  
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018  
Retransmit Capability  
Reset clears data and configures FIFO, Partial Reset clears data  
but retains configuration settings  
FEATURES  
Memory storage capacity:  
IDT723663  
IDT723673  
4,096 x 36  
8,192 x 36  
Mailbox bypass registers for each FIFO  
Free-running CLKA and CLKB may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
Clock frequencies up to 83 MHz (8 ns access time)  
Clocked FIFO buffering data from Port A to Port B  
IDT Standard timing (using EF and FF) or First Word Fall  
Through Timing (using OR and IR flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has  
five default offsets (8, 16, 64, 256 and 1,024)  
Serial or parallel programming of partial flags  
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits  
(byte)  
Easily expandable in width and depth  
Auto power down minimizes power dissipation  
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
Pin compatible with the lower density parts, IDT723633/723643  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
Big- or Little-Endian format for word and byte bus sizes  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
W/RA  
ENA  
MBA  
Port-A  
Control  
Logic  
36  
RAM ARRAY  
4,096 x 36  
8,192 x 36  
36  
36  
FIFO1  
Mail1,  
Mail2,  
Reset  
Logic  
RS1  
RS2  
PRS  
36  
RT  
RTM  
FIFO  
Retransmit  
Logic  
Read  
Pointer  
Write  
Pointer  
A0-A35  
B0-B35  
Status Flag  
Logic  
EF/OR  
AE  
FF/IR  
AF  
36  
36  
FS2  
FS0/SD  
FS1/SEN  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
13  
CLKB  
CSB  
W/RB  
ENB  
MBB  
BE  
Port-B  
Control  
Logic  
BM  
SIZE  
Mail 2  
Register  
5610 drw01  
MBF2  
CIDTOandMtheMIDTElogRoaCrereIgAisteLredtrTadeEmaMrksPofInEtegRratAedTDevUiceRTeEchnoloRgy,AIncN.SyGncFEIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
FEBRUARY 2018  
1
DSC-5610/8  

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