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IDT72275L15TF PDF预览

IDT72275L15TF

更新时间: 2024-01-24 05:17:09
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
25页 227K
描述
CMOS SUPERSYNC FIFO⑩

IDT72275L15TF 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:STQFP-64针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.9
最长访问时间:10 ns其他特性:RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH
最大时钟频率 (fCLK):66.7 MHz周期时间:15 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm内存密度:589824 bit
内存集成电路类型:OTHER FIFO内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:64字数:32768 words
字数代码:32000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:32KX18可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.02 A子类别:FIFOs
最大压摆率:0.09 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:10 mmBase Number Matches:1

IDT72275L15TF 数据手册

 浏览型号IDT72275L15TF的Datasheet PDF文件第2页浏览型号IDT72275L15TF的Datasheet PDF文件第3页浏览型号IDT72275L15TF的Datasheet PDF文件第4页浏览型号IDT72275L15TF的Datasheet PDF文件第5页浏览型号IDT72275L15TF的Datasheet PDF文件第6页浏览型号IDT72275L15TF的Datasheet PDF文件第7页 
CMOS SUPERSYNC FIFO™  
32,768 x 18  
PRELIMINARY  
IDT72275  
65,536 x 18  
IDT72285  
Integrated Device Technology, Inc.  
• Independent Read and Write Clocks (permit reading and  
writing simultaneously)  
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the  
64-pin Slim Thin Quad Flat Pack (STQFP)  
FEATURES:  
• Choose among the following memory organizations:  
IDT72275  
IDT72285  
32,768 x 18  
65,536 x 18  
• High-performance submicron CMOS technology  
• Pin-compatible with the IDT72255LA/72265LA SuperSync  
FIFOs  
• 10ns read/write cycle time (6.5ns access time)  
• Fixed, low first word data latency time  
• Auto power down minimizes standby power consumption  
• Master Reset clears entire FIFO  
• Partial Reset clears data, but retains programmable  
settings  
• Retransmit operation with fixed, low first word data  
latency time  
• Empty, Full and Half-Full flags signal FIFO status  
• Programmable Almost-Empty and Almost-Full flags, each  
flag can default to one of two preselected offsets  
• Program partial flags by either serial or parallel means  
• Select IDT Standard timing (using EF and FF flags) or First  
Word Fall Through timing (using OR and IR flags)  
DESCRIPTION:  
The IDT72275/72285 are exceptionally deep, high speed,  
CMOS First-In-First-Out (FIFO) memories with clocked read  
and write controls. These FIFOs offer numerous improve-  
mentsoverpreviousSuperSyncFIFOs,includingthefollowing:  
• The limitation of the frequency of one clock input with  
respect to the other has been removed. The Frequency  
Select pin (FS) has been removed, thus it is no longer  
necessary to select which of the two clock inputs, RCLK or  
WCLK, is running at the higher frequency.  
• The period required by the retransmit operation is now fixed  
and short.  
• The first word data latency period, from the time the first  
word is written to an empty FIFO to the time it can be read,  
is now fixed and short. (The variable clock cycle counting  
Output enable puts data outputs into high impedance state  
• Easily expandable in depth and width  
FUNCTIONAL BLOCK DIAGRAM  
D0 -D17  
WCLK  
OFFSET REGISTER  
INPUT REGISTER  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
FWFT/SI  
RAM ARRAY  
32,768 x 18  
65,536 x 18  
WRITE POINTER  
READ POINTER  
READ  
CONTROL  
LOGIC  
OUTPUT REGISTER  
RESET  
LOGIC  
RCLK  
4674 drw 01  
Q0 -Q17  
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGE  
SEPTEMBER 1998  
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.  
©1998 Integrated Device Technology, Inc  
DSC-4674/-  
1

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