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IDT72275L15PFI PDF预览

IDT72275L15PFI

更新时间: 2024-01-10 17:03:22
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
25页 227K
描述
FIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64

IDT72275L15PFI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:STQFP-64针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.9
最长访问时间:10 ns其他特性:RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH
最大时钟频率 (fCLK):66.7 MHz周期时间:15 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm内存密度:589824 bit
内存集成电路类型:OTHER FIFO内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:64字数:32768 words
字数代码:32000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:32KX18可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.02 A子类别:FIFOs
最大压摆率:0.09 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:10 mmBase Number Matches:1

IDT72275L15PFI 数据手册

 浏览型号IDT72275L15PFI的Datasheet PDF文件第1页浏览型号IDT72275L15PFI的Datasheet PDF文件第3页浏览型号IDT72275L15PFI的Datasheet PDF文件第4页浏览型号IDT72275L15PFI的Datasheet PDF文件第5页浏览型号IDT72275L15PFI的Datasheet PDF文件第6页浏览型号IDT72275L15PFI的Datasheet PDF文件第7页 
IDT72275/72285 SUPERSYNC FIFO™  
32,768 x 18, 65,536 x 18  
COMMERCIAL TEMPERATURE RANGE  
DESCRIPTION (Continued)  
There are two possible timing modes of operation with  
thesedevices:IDTStandardmodeandFirstWordFallThrough  
(FWFT) mode.  
delay associated with the latency period found on previous  
SuperSync devices has been eliminated on this SuperSync  
family.)  
In IDT Standard mode, the first word written to an empty  
FIFO will not appear on the data output lines unless a specific  
read operation is performed. A read operation, which consists  
of activating REN and enabling a rising RCLK edge, will shift  
the word from internal memory to the data output lines.  
In FWFT mode, the first word written to an empty FIFO is  
clocked directly to the data output lines after three transitions  
of the RCLK signal. A REN does not have to be asserted for  
accessing the first word. However, subsequent words written  
to the FIFO do require a LOW on REN for access. The state  
of the FWFT/SI input during Master Reset determines the  
timing mode in use.  
SuperSync FIFOs are particularly appropriate for network,  
video, telecommunications, data communications and other  
applications that need to buffer large amounts of data.  
The input port is controlled by a Write Clock (WCLK) input  
and a Write Enable (WEN) input. Data is written into the FIFO  
on every rising edge of WCLK when WEN is asserted. The  
output port is controlled by a Read Clock (RCLK) input and  
ReadEnable(REN)input. DataisreadfromtheFIFOonevery  
risingedgeofRCLKwhen RENisasserted. AnOutputEnable  
(OE) input is provided for three-state control of the outputs.  
The frequencies of both the RCLK and the WCLK signals  
may vary from 0 to fMAX with complete independence. There  
are no restrictions on the frequency of the one clock input with  
respect to the other.  
For applications requiring more data storage capacity than  
a single FIFO can provide, the FWFT timing mode permits  
depth expansion by chaining FIFOs in series (i.e. the data  
PIN CONFIGURATIONS  
PIN 1  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
Q17  
Q16  
GND  
Q15  
Q14  
2
3
DC  
4
V
CC  
GND  
D17  
D16  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
5
6
V
CC  
7
Q13  
Q12  
Q11  
GND  
Q10  
Q9  
8
9
10  
11  
12  
13  
14  
15  
16  
Q8  
Q7  
D8  
Q6  
D7  
GND  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
4674 drw 02  
TQFP (PN64-1, order code: PF)  
STQFP (PP64-1, order code: TF)  
TOP VIEW  
2

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