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IDT72261LA20PFI PDF预览

IDT72261LA20PFI

更新时间: 2024-01-30 22:26:57
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
27页 300K
描述
CMOS SuperSync FIFO

IDT72261LA20PFI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:STQFP-64针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.22
最长访问时间:12 ns其他特性:RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH
最大时钟频率 (fCLK):50 MHz周期时间:20 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm内存密度:147456 bit
内存集成电路类型:OTHER FIFO内存宽度:9
湿度敏感等级:3功能数量:1
端子数量:64字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:16KX9可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.017 A子类别:FIFOs
最大压摆率:0.075 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:10 mmBase Number Matches:1

IDT72261LA20PFI 数据手册

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CMOS SuperSync FIFO™  
16,384 x 9  
32,768 x 9  
IDT72261LA  
IDT72271LA  
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-  
pin Slim Thin Quad Flat Pack (STQFP)  
High-performance submicron CMOS technology  
Industrial temperature range (–40°C to +85°C) is available  
FEATURES:  
Choose among the following memory organizations:  
IDT72261LA 16,384 x 9  
IDT72271LA 32,768 x 9  
Pin-compatible with the IDT72281/72291 SuperSync FIFOs  
10ns read/write cycle time (8ns access time)  
Fixed, low first word data latency time  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
Partial Reset clears data, but retains programmable settings  
Retransmit operation with fixed, low first word data latency time  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag  
can default to one of two preselected offsets  
Program partial flags by either serial or parallel means  
Select IDT Standard timing (using EF and FF flags) or First  
Word Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
DESCRIPTION:  
The IDT72261LA/72271LA are exceptionally deep, high speed, CMOS  
First-In-First-Out (FIFO) memories with clocked read and write controls.  
These FIFOs offer numerous improvements over previous SuperSync  
FIFOs, including the following:  
Thelimitationofthefrequencyofoneclockinputwithrespecttotheother  
has been removed. The Frequency Select pin (FS) has been removed,  
thus it is no longer necessary to select which of the two clock inputs,  
RCLK or WCLK, is running at the higher frequency.  
The period required by the retransmit operation is now fixed and short.  
The first word data latency period, from the time the first word is written  
to an empty FIFO to the time it can be read, is now fixed and short. (The  
variableclockcyclecountingdelayassociatedwiththelatencyperiodfound  
on previous SuperSync devices has been eliminated on this SuperSync  
family.)  
Independent Read and Write clocks (permit reading and writing  
simultaneously)  
FUNCTIONAL BLOCK DIAGRAM  
D0 -D8  
WEN  
WCLK  
LD  
SEN  
OFFSET REGISTER  
INPUT REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
HF  
FWFT/SI  
RAM ARRAY  
16,384 x 9  
32,768 x 9  
WRITE POINTER  
READ POINTER  
READ  
CONTROL  
LOGIC  
RT  
OUTPUT REGISTER  
MRS  
PRS  
RESET  
LOGIC  
RCLK  
REN  
Q0 -Q8  
4671 drw 01  
OE  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
SEPTEMBER 2002  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4671/2  

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