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IDT72264L15G PDF预览

IDT72264L15G

更新时间: 2024-01-06 19:27:58
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
31页 395K
描述
VARIABLE WIDTH SUPERSYNCO FIFO 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9

IDT72264L15G 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:STQFP-64
针数:64Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:10 ns
其他特性:RETRANSMIT; AUTO POWER-DOWN备用内存宽度:9
最大时钟频率 (fCLK):66.7 MHz周期时间:15 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm内存密度:147456 bit
内存集成电路类型:OTHER FIFO内存宽度:9
湿度敏感等级:3功能数量:1
端子数量:64字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16KX9输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP64,.47SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:FIFOs最大压摆率:0.135 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:10 mm

IDT72264L15G 数据手册

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IDT72264  
IDT72274  
VARIABLE WIDTH SUPERSYNC FIFO  
8,192 x 18 or 16,384 x 9  
16,384 x 18 or 32,768 x 9  
Integrated Device Technology, Inc.  
• Industrial temperature range (-40OC to +85OC) is avail-  
able, tested to military electrical specifications  
FEATURES:  
• Select 8192 x 18 or 16384x 9 organization (IDT72264)  
• Select 16384 x 18 or 32678 x 9 organization (IDT72274)  
• Flexible control of read and write clock frequencies  
• Reduced dynamic power dissipation  
• Auto power down minimizes power consumption  
• 15 ns read/write cycle time (10 ns access time)  
• Retransmit Capability  
DESCRIPTION:  
The IDT72264/72274 are monolithic, CMOS, high capac-  
ity, high speed, low power first-in, first-out (FIFO) memories  
withclockedreadandwritecontrols. TheseFIFOshave three  
mainfeaturesthatdistinguishthemamongSuperSyncFIFOs:  
First, the data path width can be changed from 9-bits to 18-  
bits; as a result, halving the depth. A pin called Memory Array  
Select (MAC) choosesbetweenthetwooptions. Thisfeature  
helpsreducetheneedforredesignsormultipleversionsofPC  
cards, since a single layout can be used for both data bus  
widths.  
Second, IDT72264/72274 offer the greatest flexibility for  
setting and varying the read and write clock (WCLK and  
RCLK) frequencies. For example, given that the two clock  
frequencies are unequal, the slower clock may exceed the  
faster by, at most, twice its frequency. This feature is espe-  
cially useful for communications and network applications  
where clock frequencies are switched to permit different data  
rates.  
• Master Reset clears entire FIFO, Partial Reset clears  
data, but retains programmable settings  
• Empty, full and half-full flags signal FIFO status  
• Programmable almost empty and almost full flags, each  
flag can default to one of two preselected offsets  
• Program partial flags by either serial or parallel means  
• Select IDT Standard timing (using EF and FF flags) or  
First Word Fall Through timing (using OR and IR flags)  
• Easily expandable in depth and width  
• Independent read and write clocks (permits simultaneous  
reading and writing with one clock signal)  
• Available in the 64-pin Thin Quad Flat Pack (TQFP), 64-  
pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin  
Pin Grid Array (PGA)  
• Output enable puts data outputs into high impedance  
• High-performance submicron CMOS technology  
FUNCTIONAL BLOCK DIAGRAM  
D0-Dn  
WEN  
WCLK  
LD SEN  
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
FLAG  
LOGIC  
EF/OR  
WRITE CONTROL  
LOGIC  
PAE  
HF  
RAM ARRAY  
FWFT/SI  
8192 x 18 or 16384 x 9  
16384 x 18 or 32768 x 9  
WRITE POINTER  
READ POINTER  
READ  
CONTROL  
LOGIC  
MEMORY ARRAY  
CONFIGURATION  
RT  
MAC  
OUTPUT REGISTER  
MRS  
PRS  
RESET  
LOGIC  
RCLK  
REN  
TIMING  
FS  
Q0-Qn  
OE  
3218 drw 01  
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGES  
MAY 1997  
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.  
1997 Integrated Device Technology, Inc  
DSC-3218/2  
1

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