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IDT71V35761SA166PFGI8 PDF预览

IDT71V35761SA166PFGI8

更新时间: 2024-02-18 10:16:04
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
21页 972K
描述
3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

IDT71V35761SA166PFGI8 数据手册

 浏览型号IDT71V35761SA166PFGI8的Datasheet PDF文件第2页浏览型号IDT71V35761SA166PFGI8的Datasheet PDF文件第3页浏览型号IDT71V35761SA166PFGI8的Datasheet PDF文件第4页浏览型号IDT71V35761SA166PFGI8的Datasheet PDF文件第5页浏览型号IDT71V35761SA166PFGI8的Datasheet PDF文件第6页浏览型号IDT71V35761SA166PFGI8的Datasheet PDF文件第7页 
                                                                                         
                                                                                         
               
               
                                                                                         
                                                                                         
               
               
                                                                                         
                                                                                         
                                                                                         
                                                                                         
                                                                                         
                                                                                         
               
               
                                                                                         
                                                                                         
               
               
128K x 36  
IDT71V35761S/SA  
3.3VSynchronousSRAMs  
3.3VI/O,PipelinedOutputs  
BurstCounter,SingleCycleDeselect  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Features  
128K x 36 memory configurations  
Supports high system speed:  
3.3V I/O  
Commercial:  
– 200MHz 3.1ns clock access time  
CommercialandIndustrial:  
– 183MHz 3.3ns clock access time  
– 166MHz 3.5ns clock access time  
LBO input selects interleaved or linear burst mode  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1  
compliant)  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine  
pitch ball grid array  
Green parts available, see ordering information  
3.3V core power supply  
FunctionalBlockDiagram  
LBO  
ADV  
INTERNAL  
ADDRESS  
CEN  
128K x 36-  
BIT  
MEMORY  
ARRAY  
CLK  
2
Burst  
Logic  
17/18  
Binary  
Counter  
ADSC  
A0*  
A1*  
Q0  
Q1  
CLR  
ADSP  
2
CLK EN  
A0,A1  
A2–A17  
A0 - A16/17  
GW  
ADDRESS  
REGISTER  
36  
36  
17/18  
Byte 1  
Write Register  
BWE  
Byte 1  
Write Driver  
BW1  
BW2  
9
9
Byte 2  
Write Register  
Byte 2  
Write Driver  
Byte 3  
Write Register  
Byte 3  
Write Driver  
BW3  
BW4  
9
9
Byte 4  
Write Register  
Byte 4  
Write Driver  
OUTPUT  
REGISTER  
CE  
Q
D
CS0  
Enable  
Register  
CLK EN  
DATA  
INPUT  
REGISTER  
CS1  
ZZ  
Powerdown  
D
Q
Enable  
Delay  
Register  
OE  
OUTPUT  
BUFFER  
OE  
,
36  
I/O0 — I/O31  
I/OP1 — I/OP4  
5301 drw 01  
TMS  
TDI  
TCK  
JTAG  
(SA Version)  
TDO  
TRST  
(Optional)  
NOVEMBER2014  
1
©2014 Integrated Device Technology, Inc.  
DSC-5301/07  

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