IDT7143SA35GGI

更新时间： 2024-11-30 13:01:35

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	141K
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中文翻译

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数据手册

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IDT7143SA35GGI 数据手册

IDT7133SA/LA

IDT7143SA/LA

HIGH SPEED

2K X 16 DUAL-PORT

SRAM

Features

◆

High-speed access

BUSY output flag on IDT7133; BUSY input on IDT7143

Fully asynchronous operation from either port

◆

–

Military:25/35/45/55/70/90ns(max.)

Industrial:25/35/55ns(max.)

Commercial:20/25/35/45/55/70/90ns(max.)

Battery backup operation–2V data retention

TTL-compatible; single 5V (±10%) power supply

Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-

pin TQFP

Military product compliant to MIL-PRF-38535 QML

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

Low-power operation

–

IDT7133/43SA

◆

Active:1150mW(typ.)

Standby: 5mW (typ.)

IDT7133/43LA

–

Active:1050mW(typ.)

Standby: 1mW (typ.)

Versatile control for write: separate write control for lower

and upper byte of each port

MASTER IDT7133 easily expands data bus width to 32 bits

or more using SLAVE IDT7143

On-chip port arbitration logic (IDT7133 only)

Description

◆

The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs.

The IDT7133is designedtobe usedas a stand-alone 16-bitDual-Port

RAM or as a “MASTER” Dual-Port RAM together with the IDT7143

“SLAVE” Dual-Port in 32-bit-or-more word width systems. Using the

IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider

Functional Block Diagram

R/W^RUB

CER

R/WLUB

CE^L

R/WLLB

OEL

R/WRLB

OER

I/O8R - I/O15R

I/O0R - I/O7R

I/O8L - I/O15L

I/O0L - I/O7L

I/O

CONTROL

I/O

CONTROL

(1)

BUSY^R

BUSYL

A10R

A10L

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

A0L

A^0R

ARBITRATION

LOGIC

CER

CEL

(IDT7133 ONLY)

2746 drw 01

NOTE:

1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.

IDT7143 (SLAVE): BUSY is input.

JUNE 2000

DSC 2746/11

12 3 4 5 6 7...16

中文翻译

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