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IDT7134SA70JG PDF预览

IDT7134SA70JG

更新时间: 2024-11-15 19:42:11
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
11页 99K
描述
Dual-Port SRAM, 4KX8, 70ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, MS-018AD, LCC-52

IDT7134SA70JG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:LCC
包装说明:QCCJ, LDCC52,.8SQ针数:52
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.04
最长访问时间:70 ns其他特性:AUTOMATIC POWER-DOWN
I/O 类型:COMMONJESD-30 代码:S-PQCC-J52
JESD-609代码:e3长度:19.1262 mm
内存密度:32768 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8湿度敏感等级:1
功能数量:1端口数量:2
端子数量:52字数:4096 words
字数代码:4000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC52,.8SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:4.57 mm
最大待机电流:0.015 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.24 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:19.1262 mm
Base Number Matches:1

IDT7134SA70JG 数据手册

 浏览型号IDT7134SA70JG的Datasheet PDF文件第2页浏览型号IDT7134SA70JG的Datasheet PDF文件第3页浏览型号IDT7134SA70JG的Datasheet PDF文件第4页浏览型号IDT7134SA70JG的Datasheet PDF文件第5页浏览型号IDT7134SA70JG的Datasheet PDF文件第6页浏览型号IDT7134SA70JG的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7134SA/LA  
4K x 8 DUAL-PORT  
STATIC SRAM  
Features  
Fully asynchronous operation from either port  
High-speed access  
Battery backup operation2V data retention (LA only)  
TTL-compatible; single 5V (±10%) power supply  
Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available for  
selected speeds  
Military: 25/35/45/55/70ns (max.)  
Industrial:25/35/55ns(max.)  
– Commercial: 20/25/35/45/55/70ns (max.)  
Low-power operation  
IDT7134SA  
Active: 700mW (typ.)  
Standby: 5mW (typ.)  
IDT7134LA  
Green parts available, see ordering information  
Active: 700mW (typ.)  
Standby: 1mW (typ.)  
Functional Block Diagram  
R/W  
L
R/W  
CE  
R
R
CEL  
OEL  
OER  
I/O  
CONTROL  
I/O  
CONTROL  
I/O0L- I/O7L  
I/O0R- I/O7R  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
MEMORY  
ARRAY  
A0L- A11L  
A0R- A11R  
2720 drw 01  
JANUARY 2006  
1
©2006IntegratedDeviceTechnology,Inc.  
DSC-2720/13  

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