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IDT7134LA20JG PDF预览

IDT7134LA20JG

更新时间: 2024-12-01 15:46:19
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
12页 116K
描述
Dual-Port SRAM, 4KX8, 20ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, MS-018AD, LCC-52

IDT7134LA20JG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:LCC
包装说明:QCCJ, LDCC52,.8SQ针数:52
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.06
最长访问时间:20 nsI/O 类型:COMMON
JESD-30 代码:S-PQCC-J52JESD-609代码:e3
长度:19.1262 mm内存密度:32768 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
湿度敏感等级:1功能数量:1
端口数量:2端子数量:52
字数:4096 words字数代码:4000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC52,.8SQ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:4.57 mm最大待机电流:0.0015 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.24 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:19.1262 mmBase Number Matches:1

IDT7134LA20JG 数据手册

 浏览型号IDT7134LA20JG的Datasheet PDF文件第2页浏览型号IDT7134LA20JG的Datasheet PDF文件第3页浏览型号IDT7134LA20JG的Datasheet PDF文件第4页浏览型号IDT7134LA20JG的Datasheet PDF文件第5页浏览型号IDT7134LA20JG的Datasheet PDF文件第6页浏览型号IDT7134LA20JG的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7134SA/LA  
4K x 8 DUAL-PORT  
STATIC SRAM  
Š
Features  
Fully asynchronous operation from either port  
High-speed access  
Battery backup operation—2V data retention (LA only)  
TTL-compatible; single 5V (±10%) power supply  
Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available for  
selected speeds  
– Military:35/45/55/70ns(max.)  
– Industrial: 25/55ns(max.)  
– Commercial: 20/25/35/45/55/70ns (max.)  
Low-power operation  
– IDT7134SA  
Active: 700mW (typ.)  
Standby: 5mW (typ.)  
– IDT7134LA  
Green parts available, see ordering information  
Active: 700mW (typ.)  
Standby: 1mW (typ.)  
Functional Block Diagram  
R/W  
L
R/W  
R
R
CE  
CEL  
OEL  
OER  
I/O  
CONTROL  
I/O  
CONTROL  
I/O0L- I/O7L  
I/O0R- I/O7R  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
MEMORY  
ARRAY  
A0L- A11L  
A0R- A11R  
2720 drw 01  
FEBRUARY 2013  
1
©2012IntegratedDeviceTechnology,Inc.  
DSC-2720/14  

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