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IDT71124S20YG8 PDF预览

IDT71124S20YG8

更新时间: 2024-09-29 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 81K
描述
Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

IDT71124S20YG8 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOJ
包装说明:SOJ, SOJ32,.44针数:32
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.35
Is Samacsys:N最长访问时间:20 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-J32
JESD-609代码:e3长度:20.955 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端口数量:1
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX8输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ32,.44
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:3.683 mm最大待机电流:0.01 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.14 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:10.16 mmBase Number Matches:1

IDT71124S20YG8 数据手册

 浏览型号IDT71124S20YG8的Datasheet PDF文件第2页浏览型号IDT71124S20YG8的Datasheet PDF文件第3页浏览型号IDT71124S20YG8的Datasheet PDF文件第4页浏览型号IDT71124S20YG8的Datasheet PDF文件第5页浏览型号IDT71124S20YG8的Datasheet PDF文件第6页浏览型号IDT71124S20YG8的Datasheet PDF文件第7页 
IDT71124  
CMOS Static RAM  
1 Meg (128K x 8-Bit)  
Revolutionary Pinout  
Description  
Features  
The IDT71124 is a 1,048,576-bit high-speed static RAM orga-  
nized as 128K x 8. It is fabricated using IDTs high-performance,  
high-reliability CMOS technology. This state-of-the-art technology,  
combined with innovative circuit design techniques, provides a cost-  
effective solution for high-speed memory needs. The JEDEC  
centerpower/GND pinout reduces noise generation and improves  
system performance.  
128K x 8 advanced high-speed CMOS static RAM  
JEDEC revolutionary pinout (center power/GND) for  
reduced noise.  
Equal access and cycle times  
– Commercial and Industrial: 12/15/20ns  
One Chip Select plus one Output Enable pin  
Bidirectional inputs and outputs directly TTL-compatible  
Low power consumption via chip deselect  
The IDT71124 has an output enable pin which operates as fast  
as 6ns, with address access times as fast as 12ns available. All  
bidirectional inputs and outputs of the IDT71124 are TTL-compatible  
and operation is from a single 5V supply. Fully static asynchronous  
circuitry is used; no clocks or refreshes are required for operation.  
The IDT71124 is packaged in a 32-pin 400 mil Plastic SOJ.  
Available in a 32-pin 400 mil Plastic SOJ.  
Functional Block Diagram  
A
0
1,048,576-BIT  
MEMORY ARRAY  
ADDRESS  
DECODER  
A
16  
8
8
0 7  
I/O - I/O  
I/O CONTROL  
,
8
WE  
OE  
CS  
CONTROL  
LOGIC  
3514 drw 01  
FEBRUARY 2001  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-3514/10  

IDT71124S20YG8 替代型号

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