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IDT70T3339S133BCI PDF预览

IDT70T3339S133BCI

更新时间: 2024-11-24 22:57:19
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
28页 476K
描述
HIGH-SPEED 2.5V 512/256/128K X 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

IDT70T3339S133BCI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:BGA
包装说明:LBGA, BGA256,16X16,40针数:256
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.19
最长访问时间:15 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
JESD-30 代码:S-PBGA-B256JESD-609代码:e0
长度:17 mm内存密度:9437184 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端口数量:2端子数量:256
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512KX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA256,16X16,40
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:2.5,2.5/3.3 V认证状态:Not Qualified
座面最大高度:1.5 mm最大待机电流:0.02 A
最小待机电流:2.4 V子类别:SRAMs
最大压摆率:0.45 mA最大供电电压 (Vsup):2.6 V
最小供电电压 (Vsup):2.4 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:17 mmBase Number Matches:1

IDT70T3339S133BCI 数据手册

 浏览型号IDT70T3339S133BCI的Datasheet PDF文件第2页浏览型号IDT70T3339S133BCI的Datasheet PDF文件第3页浏览型号IDT70T3339S133BCI的Datasheet PDF文件第4页浏览型号IDT70T3339S133BCI的Datasheet PDF文件第5页浏览型号IDT70T3339S133BCI的Datasheet PDF文件第6页浏览型号IDT70T3339S133BCI的Datasheet PDF文件第7页 
HIGH-SPEED 2.5V  
512/256/128K X 18  
SYNCHRONOUS  
PRELIMINARY  
IDT70T3339/19/99S  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
Data input, address, byte enable and control registers  
Features:  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
Dual Cycle Deselect (DCD) for Pipelined Output Mode  
2.5V (±100mV) power supply for core  
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V  
(±100mV) power supply for I/Os and control signals on  
each port  
Industrial temperature range (-40°C to +85°C) is  
available at 166MHz and 133MHz  
Available in a 256-pin Ball Grid Array (BGA), a 144-pin Thin  
Quad Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array  
(fpBGA)  
Supports JTAG features compliant with IEEE 1149.1  
Due to limited pin count JTAG, Collision Detection and  
Interrupt are not supported on the 144-pin TQFP package  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed data access  
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/  
4.2ns (133MHz)(max.)  
Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)  
Selectable Pipelined or Flow-Through output mode  
Counter enable and repeat features  
Dual chip enables allow for depth expansion without  
additional logic  
Interrupt and Collision Detection Flags  
Full synchronous operation on both ports  
– 5ns cycle time, 200MHzoperation(14Gbps bandwidth)  
– Fast 3.4ns clock to data out  
– 1.5ns setup to clock and 0.5ns hold on all control, data, and  
address inputs @ 200MHz  
FunctionalBlockDiagram  
UBL  
UBR  
LBL  
LBR  
FT/PIPE  
L
1b 0b  
b
1a 0a  
a
0a 1a  
a
0b 1b  
b
FT/PIPER  
1/0  
1/0  
R/W  
CE0L  
L
R/  
WR  
CE0R  
1
1
CE1R  
CE1L  
B
W
0
B
W
1
B B  
0
0
W W  
1
0
L
L
R
R
1/0  
1/0  
Dout0-8_L  
Dout9-17_L  
Dout0-8_R  
Dout9-17_R  
OE  
L
OE  
R
,
0a 1a  
0b  
1b  
1b 0b 1a 0a  
ab  
0/1  
FT/PIPE  
R
FT/PIPE  
L
0/1  
ba  
512/256/128K x 18  
MEMORY  
ARRAY  
I/O0R - I/O17R  
Din_L  
I/O0L - I/O17L  
Din_R  
,
CLK  
R
CLK  
L
(1)  
18R  
(1)  
18L  
A
A
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A
0L  
REPEAT  
ADS  
CNTEN  
A
0R  
REPEAT  
ADS  
CNTEN  
ADDR_R  
ADDR_L  
L
R
R
L
R
L
TDI  
TCK  
TMS  
TRST  
INTERRUPT  
CE  
0
CE  
0
R
R
JTAG  
L
COLLISION  
DETECTION  
LOGIC  
CE1  
TDO  
CE1  
L
R/W  
R
R/  
W
L
COL  
INTL  
L
COLR  
INTR  
5652 drw 01  
(2)  
(2)  
ZZR  
ZZ  
ZZ  
L
CONTROL  
LOGIC  
NOTES:  
1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.  
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and  
NOVEMBER 2003  
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.  
1
DSC-5652/3  
©2003 IntegratedDeviceTechnology,Inc.  

IDT70T3339S133BCI 替代型号

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