Datasheet > IDT709389L9PF

IDT709389L9PF

更新时间： 2024-09-30 23:57:59

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器时钟
页数	文件大小	规格书
15页	191K
描述
x18 Dual-Port SRAM

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中文翻译

获取价格

数据手册

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IDT709389L9PF 数据手册

HIGH-SPEED 64K x 18

IDT709389L

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial: 7.5/9/12ns (max.)

Low-power operation

Full synchronous operation on both ports

– 4ns setup to clock and 0ns hold on all control, data, and

address inputs

◆

– Data input, address, and control registers

– Fast 7.5ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– IDT709389L

Active: 1.2W (typ.)

Standby: 2.5mW (typ.)

– 12ns cycle time, 83MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

TTL- compatible, single 5V (±10%) power supply

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

◆

Flow-Through or Pipelined output mode on either Port via

the FT/PIPE pins

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

◆

Available in a 100-pin Thin Quad Flatpack (TQFP) package

Functional Block Diagram

R/WL

R/WR

UBR

CE0L

CE1L

CE0R

CE1R

0/1

LBL

LBR

OEL

OER

1b 0b

0a 1a

0b 1b

1a 0a

FT/PIPEL

0/1

FT/PIPER

I/O9L-I/O17L

I/O0L-I/O8L

I/O_9R-I/O_17R

I/O0R-I/O8R

I/O

Control

I/O

Control

A15R

A15L

Counter/

Address

Reg.

Counter/

Address

Reg.

MEMORY

ARRAY

A0R

A0L

CLKL

ADSL

CLKR

ADSR

CNTENR

CNTEN

CNTRSTL

CNTRSTR

4844 drw 01

JANUARY 2001

DSC-4844/3

12 3 4 5 6 7...15

中文翻译

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