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IDT7024S15FG PDF预览

IDT7024S15FG

更新时间: 2024-12-01 20:07:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 180K
描述
Dual-Port SRAM, 4KX16, 15ns, CMOS, 1.170 X 1.170 INCH, 0.110 INCH HEIGHT, GREEN, QFP-84

IDT7024S15FG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:QFF, QFL84,1.2SQ针数:84
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.17
最长访问时间:15 nsI/O 类型:COMMON
JESD-30 代码:S-XQFP-F84JESD-609代码:e3
长度:29.21 mm内存密度:65536 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
功能数量:1端口数量:2
端子数量:84字数:4096 words
字数代码:4000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX16输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:QFF
封装等效代码:QFL84,1.2SQ封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:3.556 mm
最大待机电流:0.000015 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.31 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:FLAT
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:29.21 mm
Base Number Matches:1

IDT7024S15FG 数据手册

 浏览型号IDT7024S15FG的Datasheet PDF文件第2页浏览型号IDT7024S15FG的Datasheet PDF文件第3页浏览型号IDT7024S15FG的Datasheet PDF文件第4页浏览型号IDT7024S15FG的Datasheet PDF文件第5页浏览型号IDT7024S15FG的Datasheet PDF文件第6页浏览型号IDT7024S15FG的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7024S/L  
4K x 16 DUAL-PORT  
STATIC RAM  
IDT7024 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = H for BUSY output flag on Master  
M/S = L for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Battery backup operation2V data retention  
TTL-compatible, single 5V (±10%) power supply  
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin  
Quad Flatpack  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Green parts availble, see ordering information  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
Military:20/25/35/55/70ns(max.)  
Industrial:55ns (max.)  
– Commercial:15/17/20/25/35/55ns(max.)  
Low-power operation  
IDT7024S  
Active:750mW(typ.)  
Standby: 5mW (typ.)  
IDT7024L  
Active:750mW(typ.)  
Standby: 1mW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
FunctionalBlockDiagram  
R/W  
L
R/W  
R
R
UB  
UBL  
LB  
CE  
OE  
L
L
L
LBR  
CE  
R
R
OE  
I/O8L-I/O15L  
I/O0L-I/O7L  
I/O8R-I/O15R  
I/O  
Control  
I/O  
Control  
I/O0R-I/O7R  
BUSY (1,2)  
L
BUSYR  
(1,2)  
A
11R  
0R  
A
11L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
12  
12  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/W  
R
CE  
OE  
R/W  
L
L
R
R
L
SEM  
R
SEM  
L
(2)  
INT (2)  
L
M/S  
INTR  
2740 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
OCTOBER 2008  
1
DSC 2740/13  
©2008IntegratedDeviceTechnology,Inc.  

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