Datasheet > IDT5T9010BBGI8

IDT5T9010BBGI8

更新时间： 2024-02-14 14:51:45

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
23页	168K
描述
PLL Based Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), PBGA144, LEAD FREE, PLASTIC, BGA-144

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

IDT5T9010BBGI8 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA, BGA144,12X12,40	针数：	144
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	Is Samacsys：	N
系列：	5T	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-PBGA-B144	JESD-609代码：	e1
长度：	13 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.008 A	湿度敏感等级：	3
功能数量：	1	反相输出次数：
端子数量：	144	实输出次数：	5
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA144,12X12,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	260	电源：	1.5/2.5,2.5 V
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.1 ns
座面最大高度：	1.97 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	13 mm	最小 fmax：	250 MHz
Base Number Matches：	1

IDT5T9010BBGI8 数据手册

IDT5T9010

INDUSTRIALTEMPERATURERANGE

2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK

PROGRAMMABLESKEW

Output skew with respect to the REF[1:0] and REF[1:0]/VREF[1:0] input by the nF[2:0]/FBF[2:0] control pins. In order to minimize the number of

is adjustable to compensate for PCB trace delays, backplane propaga- control pins, 3-level inputs (HIGH-MID-LOW) are used, they are in-

tion delays or to accommodate requirements for special timing relation- tended for but not restricted to hard-wiring. Undriven 3-level inputs

ships between clocked components. Skew is selectable as a multiple of a default to the MID level. The Control Summary Table shows how to

time unit (tU) which ranges from 250ps to 1.25ns (see Programmable select specific skew taps by using the nF[2:0]/FBF[2:0] control pins.

Skew Range and Resolution Table). There are 18 skew/divide configu-

rations available for each output pair. These configurations are chosen

EXTERNALDIFFERENTIALFEEDBACK

By providing a dedicated external differential feedback, the IDT5T9010

An internal loop filter moderates the response of the VCO to the

gives users flexibility with regard to skew adjustment. The FB and FB/ phase detector. The loop filter transfer function has been chosen to

VREF2 signals are compared with the input REF[1:0] and REF[1:0]/VREF[1:0] provide minimal jitter (or frequency variation) while still providing accu-

signals at the phase detector in order to drive the VCO. Phase differ- rate responses to input frequency changes.

ences cause the VCO of the PLL to adjust upwards or downwards

accordingly.

PROGRAMMABLESKEWRANGEANDRESOLUTIONTABLE

FS = LOW

1/(16 x FNOM)

50 to 125MHz

FS = HIGH

1/(16 x FNOM)

100 to 250MHz

Comments

TimingUnitCalculation(tU)

VCOFrequencyRange(FNOM)^(1,2)

SkewAdjustmentRange⁽³⁾

MaxAdjustment:

±8.75ns

±157.5°

±43.75%

tU =1.25ns

tU =0.833ns

tU =0.625ns

—

±4.375ns

±157.5°

PhaseDegrees

% of Cycle Time

±43.75%

—

Example 1, FNOM = 50MHz

Example 2, FNOM = 75MHz

Example 3, FNOM = 100MHz

Example 4, FNOM = 150MHz

Example 5, FNOM = 200MHz

Example 6, FNOM = 250MHz

—

tU =0.625ns

tU =0.417ns

tU =0.313ns

tU =0.25ns

—

NOTES:

1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.

2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at nQ[1:0] outputs when

they are operated in their undivided modes. The frequency appearing at the REF[1:0] and REF[1:0]/VREF[1:0] and FB and FB/VREF2 inputs will be FNOM when the QFB and QFB

are undivided and DS[1:0] = MM. The frequency of the REF[1:0] and REF[1:0]/VREF[1:0] and FB and FB/VREF2 inputs will be FNOM /2 or FNOM /4 when the part is configured for

frequency multiplication by using a divided QFB and QFB and setting DS[1:0] = MM. Using the DS[1:0] inputs allows a different method for frequency multiplication (see Divide

Selection Table).

3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed QFB and QFB output is used for feedback, then adjustment range will be greater.

For example if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’

range applies to all output pairs where ±7tU skew adjustment is possible and at the lowest FNOM value.

1 2 3 456 7 8...23

下载PDF

与IDT5T9010BBGI8相关器件

型号	品牌	描述	获取价格	数据表
IDT5T905	IDT	2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER	获取价格
IDT5T9050	IDT	2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABU	获取价格
IDT5T9050PGGI	IDT	Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, TSSOP-28	获取价格
IDT5T9050PGGI8	IDT	Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, TSSOP-28	获取价格
IDT5T9050PGI	IDT	2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABU	获取价格
IDT5T905PGGI	IDT	Low Skew Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, GR	获取价格

与IDT5T9010BBGI8相关文章

?TPA3116D2功放芯片参数详解、引脚说明
2024-06-03

1
74HC165引脚说明、驱动程序示例解读
2024-06-03

2
深入解析AD9833：DDS频率合成器的卓越性能与广泛应用
2024-06-03

2
高性能TDA7293音频功率放大器技术特性与应用分析
2024-06-03

2

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT5T9010BBGI8

IDT5T9010BBGI8 技术参数

IDT5T9010BBGI8 数据手册

与IDT5T9010BBGI8相关器件

与IDT5T9010BBGI8相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT5T9010BBGI8

IDT5T9010BBGI8 技术参数

IDT5T9010BBGI8 数据手册

与IDT5T9010BBGI8相关器件

与IDT5T9010BBGI8相关文章

您还可以找

您在本页遇到什么问题？