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IDT54FCT162701TEB PDF预览

IDT54FCT162701TEB

更新时间: 2024-11-27 21:03:07
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
9页 112K
描述
FIFO, 4X18, 6ns, Synchronous, CMOS, CDFP56, CERPACK-56

IDT54FCT162701TEB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DFP包装说明:CERPACK-56
针数:56Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:6 ns
周期时间:6 nsJESD-30 代码:R-GDFP-F56
JESD-609代码:e0长度:18.415 mm
内存密度:72 bit内存宽度:18
功能数量:1端子数量:56
字数:4 words字数代码:4
工作模式:SYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:4X18
输出特性:3-STATE可输出:YES
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL56,.4,25封装形状:RECTANGULAR
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified筛选级别:MIL-STD-883 Class B
座面最大高度:2.413 mm子类别:Other Memory ICs
最大压摆率:0.005 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:9.652 mmBase Number Matches:1

IDT54FCT162701TEB 数据手册

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IDT54/74FCT162701T/AT  
FAST CMOS 18-BIT  
R/W BUFFER  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
The FCT162701T/AT is an 18-bit Read/Write buffer with  
a four deep FIFO and a read-back latch. It can be used as  
a read/write buffer between a CPU and memory or to  
interface a high-speed bus and a slow peripheral. The A-  
to-B (write) path has a four deep FIFO for pipelined opera-  
• Typical tSK(o) (Output Skew) < 250ps  
• Low input and output leakage 1µA (max.)  
• ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
• Packagesinclude25milpitchSSOP, 19.6milpitchTSSOP, tions. The FIFO can be reset and a FIFO full condition is  
15.7 mil pitch TVSOP and 25 mil pitch Cerpack  
• Extended commercial range of -40°C to +85°C  
indicated by the full flag (FF). The B-to-A (read) path has a  
latch. A HIGH on LE, allows data to flow transparently from  
B-to-A. A LOW on LE allows the data to be latched on the  
falling edge of LE.  
• Balanced Output Drivers:  
±24mA (commercial),  
±16mA (military)  
• Reduced system switching noise  
• Typical VOLP (Output Ground Bounce) < 0.6V at  
VCC = 5V, TA = 25°C  
The FCT162701T/AT has a balanced output drive with  
series termination. This provides low ground bounce,  
minimal undershoot and controlled output edge rates.  
• Ideal for new generation x86 write-back cache solutions  
• Suitable for modular x86 architectures  
• Four deep write FIFO  
• Latch in read path  
• Synchronous FIFO reset  
FUNCTIONAL BLOCK DIAGRAM  
A1-18  
18  
OEBA  
RESET  
CLK  
LE  
FIFO  
(4 deep)  
LATCH  
WCE  
RCE  
FF  
OEAB  
18  
2915 drw 01  
B
1-18  
The IDT logo is a registered trademark of Integrated Device Techology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 1996  
1996 Integrated Device Technology, Inc.  
5.15  
DSC-2915/3  
1

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