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IDT54823CTEB PDF预览

IDT54823CTEB

更新时间： 2024-01-12 15:06:48
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
9页 182K
描述
Bus Driver, FCT Series, 1-Func, 9-Bit, True Output, CMOS, CDFP24, CERPACK-24

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IDT54823CTEB 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：24
Reach Compliance Code：unknown风险等级：5.84
其他特性：WITH CLEAR AND CLOCK ENABLE系列：FCT
JESD-30 代码：R-GDFP-F24JESD-609代码：e0
长度：15.748 mm逻辑集成电路类型：BUS DRIVER
位数：9功能数量：1
端口数量：2端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：13.5 ns认证状态：Not Qualified
座面最大高度：2.286 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：TIN LEAD
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL宽度：9.144 mm
Base Number Matches：1

IDT54823CTEB 数据手册

 浏览型号IDT54823CTEB的Datasheet PDF文件第1页浏览型号IDT54823CTEB的Datasheet PDF文件第2页浏览型号IDT54823CTEB的Datasheet PDF文件第4页浏览型号IDT54823CTEB的Datasheet PDF文件第5页浏览型号IDT54823CTEB的Datasheet PDF文件第6页浏览型号IDT54823CTEB的Datasheet PDF文件第7页 
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT  
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
PIN DESCRIPTION  
FUNCTION TABLE(1)  
Internal/  
Outputs  
Names  
I/O  
Description  
Inputs  
DI  
I
The D flip-flop data inputs.  
DI  
CP  
QI  
YI  
OE  
CLR  
EN  
Function  
CLR  
I
When the clear input is LOW and OE is  
LOW, the QI outputs are LOW. When  
the clear input is HIGH, data can be  
entered into the register.  
H
H
H
H
L
L
L
H
↑
↑
L
H
Z
Z
High Z  
H
L
L
L
X
X
H
H
L
L
L
L
X
X
X
X
L
H
L
H
X
X
X
X
↑
L
L
Z
L
Clear  
Hold  
Load  
CP  
I
Clock Pulse for the Register; enters  
data into the register on the LOW-to-  
HIGH transition.  
H
L
H
H
H
H
H
H
NC  
NC  
L
Z
NC  
Z
H
H
L
YI  
O
I
The register 3-state outputs.  
H
Z
↑
EN  
Clock Enable. When the clock enable is  
LOW, data on the D I input is transferred  
to the QI output on the LOW-to-HIGH  
clock transition. When the clock enable  
is HIGH, the QI outputs do not change  
state, regardless of the data or clock  
input transitions.  
L
L
↑
L
H
H
↑
NOTE:  
1. H = HIGH  
L = LOW  
2567 tbl 02  
X = Don’t Care  
NC = No Change  
↑ = LOW-to-HIGH Transition  
Z = High Impedance  
OE  
I
Output Control. When the OE input is  
HIGH, the Y I outputs are in the high-  
impedance state. When the OE input is  
LOW, the TRUE register data is present  
at the YI outputs.  
2567 tbl 01  
ABSOLUTE MAXIMUM RATINGS(1)  
CAPACITANCE (TA = +25°C, f = 1.0MHz)  
Symbol  
Parameter(1)  
Conditions Typ. Max. Unit  
Symbol  
Rating  
Commercial  
Military  
Unit  
(2)  
CIN  
Input  
Capacitance  
Output  
VIN = 0V  
6
8
10  
pF  
VTERM  
Terminal Voltage  
with Respect to  
GND  
–0.5 to +7.0 –0.5 to +7.0  
V
COUT  
VOUT = 0V  
12  
pF  
(3)  
VTERM  
Terminal Voltage  
with Respect to  
GND  
–0.5 to  
–0.5 to  
V
Capacitance  
VCC +0.5  
VCC +0.5  
2567 lnk 04  
NOTE:  
1. This parameter is measured at characterization but not tested.  
TA  
Operating  
0 to +70  
–55 to +125 °C  
Temperature  
Temperature  
Under Bias  
Storage  
TBIAS  
TSTG  
–55 to +125 –65 to +135 °C  
–55 to +125 –65 to +150 °C  
Temperature  
Power Dissipation  
PT  
0.5  
0.5  
W
IOUT  
DC Output  
Current  
–60 to +120 –60 to +120 mA  
2567 lnk 03  
NOTES:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-  
INGS may cause permanent damage to the device. This is a stress rating  
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions  
above those indicated in the operational sections of this specification is  
not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect reliability. No terminal voltage may exceed  
VCC by +0.5V unless otherwise noted.  
2. Input and VCC terminals only.  
3. Outputs and I/O terminals only.  
6.21  
3
1234567...9

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