Datasheet > 逻辑 > 时钟驱动器> IDT2309B-1HPGGBLANK

IDT2309B-1HPGGBLANK

更新时间： 2024-10-03 11:15:11

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
10页	272K
描述
3.3V ZERO DELAY CLOCK BUFFER

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IDT2309B

3.3VZERODELAYCLOCKBUFFER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT2309B

3.3V ZERO DELAY

CLOCK BUFFER

FEATURES:

DESCRIPTION:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five and one bank of

four outputs

The IDT2309B is a high-speed phase-lock loop (PLL) clock buffer,

designedtoaddresshigh-speedclockdistributionapplications. Thezero

delay is achieved by aligning the phase between the incoming clock and

the output clock, operable within the range of 10 to 133MHz.

• Separate output enable for each output bank

• Output Skew < 250ps

• Low jitter <175 ps cycle-to-cycle

• 50ps typical cycle-to-cycle jitter (15pF, 66MHz)

• IDT2309B-1 for Standard Drive

• IDT2309B-1H for High Drive

• No external RC network required

• Operates at 3.3V VDD

• Available in SOIC and TSSOP packages

The IDT2309B is a 16-pin version of the IDT2305B. The IDT2309B

acceptsonereferenceinput,anddrivestwobanksoffourlowskewclocks.

The -1H version of this device operates at up to 133MHz frequency and

hashigherdrivethanthe-1device. Allpartshaveon-chipPLLswhichlock

to an input clock on the REF pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad. In the absence of an input clock, the

IDT2309Benterspowerdown,andtheoutputsaretri-stated.Inthismode,

the device will draw less than 25µA.

The IDT2309B is characterized for both Industrial and Commercial

operation.

FUNCTIONALBLOCKDIAGRAM

CLKOUT

CLKA1

PLL

REF

CLKA2

CLKA3

CLKA4

Control

Logic

CLKB1

CLKB2

CLKB3

CLKB4

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

MAY 2010

2010 Integrated Device Technology, Inc.

DSC 6996/3

12 3 4 5 6 7...10

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