Datasheet > IDT2309PGGI

IDT2309PGGI

更新时间： 2024-10-03 12:02:43

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
10页	125K
描述
3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution

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IDT2309PGGI 数据手册

IDT2309

3.3VZERODELAYCLOCKBUFFER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT2309

3.3V ZERO DELAY

CLOCK BUFFER

FEATURES:

DESCRIPTION:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five and one bankd

of four outputs

The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer,

designedtoaddresshigh-speedclockdistributionapplications. Thezero

delay is achieved by aligning the phase between the incoming clock and

the output clock, operable within the range of 10 to 133MHz.

• Separate output enable for each output bank

• Output Skew < 250ps

• Low jitter <200 ps cycle-to-cycle

• IDT2309-1 for Standard Drive

• IDT2309-1H for High Drive

TheIDT2309isa16-pinversionoftheIDT2305. TheIDT2309accepts

one reference input, and drives two banks of four low skew clocks. The

-1H version of this device operates at up to 133MHz frequency and has

higher drive than the -1 device. All parts have on-chip PLLs which lock

to an input clock on the REF pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad. In the absence of an input clock, the

IDT2309 enters power down, and the outputs are tri-stated. In this mode,

• No external RC network required

• Operates at 3.3V VDD

• Available in SOIC and TSSOP packages

the device will draw less than 25µA.

The IDT2309 is characterized for both Industrial and Commercial

operation.

FUNCTIONALBLOCKDIAGRAM

CLKOUT

CLKA1

PLL

REF

CLKA2

CLKA3

CLKA4

Control

Logic

CLKB1

CLKB2

CLKB3

CLKB4

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

AUGUST 2012

2012 Integrated Device Technology, Inc.

DSC 5175/7

12 3 4 5 6 7...10

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