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IDT23S05 PDF预览

IDT23S05

更新时间: 2024-10-02 22:48:15
品牌 Logo 应用领域
艾迪悌 - IDT 时钟
页数 文件大小 规格书
8页 63K
描述
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

IDT23S05 数据手册

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IDT23S05  
3.3V ZERO DELAY CLOCK  
BUFFER, SPREAD SPECTRUM  
COMPATIBLE  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five outputs  
• Zero Input-Output Delay  
The IDT23S05 is a high-speed phase-lock loop (PLL) clock buffer,  
designed to address high-speed clock distribution applications. The zero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Output Skew < 250ps  
The IDT23S05 is an 8-pin version of the IDT23S09. IDT23S05 accepts  
one reference input, and drives out five low skew clocks. The -1H version  
ofthisdeviceoperatesupto133MHzfrequencyandhasahigherdrivethan  
the -1 device. All parts have on-chip PLLs which lock to an input clock on  
theREFpin.ThePLLfeedbackison-chipandisobtainedfromtheCLKOUT  
pad. In the absence of an input clock, the IDT23S05 enters power down.  
• Low jitter <200 ps cycle-to-cycle  
• IDT23S05-1 for Standard Drive  
• IDT23S05-1H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Power down mode  
Inthismode,thedevicewilldrawlessthan1AforCommercialTempera-  
• Spread spectrum compatible  
• Available in SOIC package  
turerangeandlessthan2AforIndustrialtemperaturerange, theoutputs  
aretri-stated,andthePLLisnotrunning,resultinginasignificantreduction  
of power.  
The IDT23S05 is characterized for both Industrial and Commercial  
operation.  
FUNCTIONALBLOCKDIAGRAM  
8
CLKOUT  
3
CLK1  
PLL  
1
Control  
Logic  
REF  
2
CLK2  
CLK3  
CLK4  
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
OCTOBER 2003  
1
c
2003 Integrated Device Technology, Inc.  
DSC 6381/6  

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