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ICSLV218RILF PDF预览

ICSLV218RILF

更新时间: 2024-09-25 21:01:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 141K
描述
Low Skew Clock Driver, 218 Series, 8 True Output(s), 0 Inverted Output(s), PDSO28, 0.150 INCH, ROHS COMPLIANT, MO-153, SSOP-28

ICSLV218RILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:0.150 INCH, ROHS COMPLIANT, MO-153, SSOP-28针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84其他特性:IT ALSO REQUIRES 2.375V TO 3.63V SUPPLY
系列:218输入调节:STANDARD
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:9.9 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:2反相输出次数:
端子数量:28实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.15 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):2.75 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mm最小 fmax:200 MHz
Base Number Matches:1

ICSLV218RILF 数据手册

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PRELIMINARY INFORMATION  
ICSLV218  
Dual 1-to-8 Low Voltage Clock Buffer/Translator  
Description  
Features  
The ICSLV218 is a high-speed clock buffer consisting  
of two independent single-input to eight-output  
low-skew, non-inverting clock drivers.  
Dual 1:8 clock drivers  
Pin-compatible with MK74CB218  
Independent supply rails on input and output banks  
for voltage translation  
The ICSLV218 has three independent supply rails: The  
input supply rail, VDDIN, operates from a fixed 2.5 V  
supply, while the output supply rails, VDDA and VDDB,  
operate from 2.5 V-3.3 V and 1.8 V-2.5 V supplies  
respectively. This configuration, combined with 3.3 V  
tolerance on the INA and INB inputs, allows for many  
different possibilities of up and/or down voltage  
translation.  
3.3 V input tolerance  
Low skew outputs within same bank (150 ps)  
Output Enable tri-states both banks of eight  
Clock speeds up to 200 MHz  
Industrial temperature range (-40 to 85°C)  
28-pin SSOP (150 mil body) Pb (lead) free package  
Block Diagram  
VDDA  
(2.5V-3.3V)  
VDDIN  
(2.5V)  
VDDB  
(1.8V-2.5V)  
(3.3V tolerant) INB  
INB (3.3V tolerant)  
QA0  
QA1  
QA2  
QA3  
QA4  
QA5  
QA6  
QA7  
QB0  
QB1  
QB2  
QB3  
QB4  
QB5  
QB6  
QB7  
OE (all outputs)  
GND  
MDS LV218 A  
1
Revision 083105  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  

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