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ICSLV810FILF PDF预览

ICSLV810FILF

更新时间: 2024-09-25 03:36:55
品牌 Logo 应用领域
矽成 - ICSI 时钟驱动器
页数 文件大小 规格书
12页 244K
描述
Buffer/Clock Driver

ICSLV810FILF 数据手册

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ICSLV810  
Buffer/Clock Driver  
Description  
Features  
The ICSLV810 is a low skew 1.5 V to 2.5 V, 1:10 fanout  
buffer. This device is specifically designed for data  
communications clock management. The large fanout  
from a single input line reduces loading on the input  
clock. The TTL level outputs reduce noise levels on the  
part. Typical applications are clock and signal  
distribution.  
Packaged in 20-pin QSOP/SSOP  
Split 1:10 fanout Buffer  
Maximum skew between outputs of different  
packages 0.75 ns  
Max propagation delay of 3.8 ns  
Operating voltage of 1.5 V to 2.5 V on Bank A  
Operating voltage of 1.5 V to 2.5 V on Banks B and C  
Advanced, low power, CMOS process  
Industrial temperature range -40° C to +85° C  
3.3 V tolerant input when VDDA=2.5 V  
Available in Pb (lead) free packaging  
Block Diagram  
VDDA  
CLK 1  
CLK 2  
CLK 3  
CLK 4  
CLK 5  
CLKIN  
CLK 6  
CLK 7  
CLK 8  
CLK 9  
CLK 10  
VDDB  
VDDC  
MDS LV810 F  
1
Revision 101305  
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  

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