Datasheet > ICS93V857G-T

ICS93V857G-T

更新时间： 2023-02-26 13:30:03

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
9页	323K
描述
Clock Driver

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数据手册

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ICS93V857G-T 数据手册

ICS93V857

Preliminary Product Preview

Timing Requirem ents

T_A= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)

CONDITIONS

PARAMETER

Operating clock frequency

Input clock duty cycle

SYMBOL

freq_op

MIN

MAX

170

UNITS

MHz

d_tin

from VDD = 3.3V to 1%

target freq.

CLK stabilization

T_STAB

100

µs

Switching Characteristics

PARAMETER

Low-to high level propagation

delay time

SYMBOL

CONDITION

MIN

TYP

3.5

MAX UNITS

CLK_IN to any output

t_PLH

High-to low level propagation

delay time

CLK_IN to any output

3.5

t_PLL

Output enable time

Output disable time

t_EN

PD# to any output

66MHz

100/125/133/167MHz

100/133/167MHz

tdis

Jitter period

T_{jit (per)}

-75

-100

100

Half-period jitter

Input clock slew rate

Output clock slew reate

t(jit_hper)

t(sir_I)

t(sl_o)

66MHz

100/125/133/167MHz

Cycle to Cycle Jitter1

T_cyc-T_cyc

Phase error

t_{(phase error)}

T_skew

-50

Output to Output Skew

Pulse skew

100

T_skewp

100

50.5

66MHz to 100MHz

101MHz to 167MHz

Load = 120 /16pF

49.5

650

Duty cycle

D_C

Rise Time, Fall Time

tr, tf

800

950

Ω

Notes:

1. Refers to transition on noninverting output in PLL bypass mode.

2. While the pulse skew is almost constant over frequency, the duty cycle error increases at

higher frequencies. This is due to the formula: duty cycle=t_wH/t_c, were the cycle (t_c)

decreases as the frequency goes up.

1 2 3 456 7 8 9

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