Datasheet > ICS93V855YGT

ICS93V855YGT

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
9页	66K
描述
PLL Based Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28

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ICS93V855YGT 数据手册

ICS93V855

DC Electrical Characteristics

TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)

SYMBOL

MIN

2.3

TYP

2.5

MAX

2.7

UNITS

PARAMETER

Supply Voltage

CONDITIONS

V_DDQ, A_VDD

CLK_INT, CLK_INC, FB_INC,

FB_INT

CLK_INT, CLK_INC, FB_INC,

V_IL

V_IH

V_IN

V_ID

V_OD

V_OX

V_IX

T_A

_DD/2 - 0.18

Low level input voltage

High level input voltage

0.4

2.1

_DD/2 + 0.18

FB_INT

DC input signal voltage (note

1,2)

Differential input signal

voltage (note 3)

Differential output voltage

(note 3)

Output differential cross-

voltage (note 4)

Input differential cross-

voltage (note 4)

Operating free-air

temperature

V_DD+ 0.3

-0.3

CLK_INT, CLK_INC, FB_INC,

FB_INT

CLK_INT, CLK_INC, FB_INC,

_DD+ 0.6

0.36

0.7

FB_INT

V_DD/2 - 0.15

V_DD/2 - 0.2

V_DD/2 + 0.15

V_DD/2 + 0.2

V_DD/2

°C

Notes:

1 Unused inputs must be held high or low to prevent them from floating.

2 DC input signal voltage specifies the allowable DC excursion of differential input.

3 Differential input signal voltage specifies the differential voltage [VTR-VCP] required for switching,

where VTR is the true input level and VCP is the complementary input level.

4 Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the

differential signal must be crossing.

0497B—06/01/04

1 2 345 6 7...9

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