Datasheet > ICS93V857G-T

ICS93V857G-T

更新时间： 2023-02-26 13:30:03

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
9页	323K
描述
Clock Driver

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ICS93V857G-T 数据手册

ICS93V857

Integrated

Circuit

Systems, Inc.

Preliminary Product Preview

DDR Phase Lock Loop Clock Driver

RecommendedApplication:

DDR Memory Modules

Pin Configuration

GND

CLKC0

CLKT0

VDD

CLKT1

CLKC1

GND

ProductDescription/Features:

CLKC5

CLKT5

VDD

CLKT6

CLKC6

GND

Low skew, low jitter PLLclock driver

1 to 10 differential clock distribution

Feedback pins for input to output synchronization

PD# for power management

GND

CLKC2

CLKT2

VDD

CLKC7

CLKT7

VDD

Spread Spectrum tolerant inputs

VDD

PD#

CLK_INT

CLK_INC

VDD

AVDD

AGND

GND

CLKC3

CLKT3

VDD

CLKT4

CLKC4

GND

FB_INT

FB_INC

VDD

FB_OUTC

FB_OUTT

GND

CLKC8

CLKT8

VDD

CLKT9

CLKC9

GND

Specifications:

Meet JEDEC standard #82 for registered DDR

clockdriver.

Switching Characteristics:

PEAK-PEAKjitter(66MHz):<120ps

PEAK-PEAKjitter(>100MHz):<75ps

CYCLE-CYCLEjitter(66MHz):<120ps

CYCLE-CYCLEjitter(>100MHz):<65ps

OUTPUT-OUTPUTskew:<100ps

Output Rise and Fall Time: 650ps - 950ps

DUTYCYCLE:49.5%-50.5%

48-Pin TSSOP

Block Diagram

FB_OUTT

FB_OUTC

CLKT0

CLKC0

Functionality

CLKT1

CLKC1

INPUTS

OUTPUTS

PLL State

Control

Logic

AVDD PD# CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC

CLKT2

CLKC2

PD#

GND

Bypassed/off

CLKT3

CLKC3

CLKT4

CLKC4

2.5V

(nom)

off

FB_INT

FB_INC

2.5V

(nom)

CLKT5

CLKC5

PLL

CLK_INC

CLK_INT

2.5V

(nom)

CLKT6

CLKC6

2.5V

(nom)

CLKT7

CLKC7

2.5V

(nom)

<20MHz)⁽¹⁾

CLKT8

CLKC8

CLKT9

CLKC9

PRODUCT PREVIEW documents contain information on new

93V857 Rev A 11/10/00

products in the sampling or preproduction phase of development.

Characteristic data and other specifications are subject to change

without notice.

12 3 4 5 6 7...9

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